ATE174699T1 - Verarbeitungssystem und -verfahren - Google Patents

Verarbeitungssystem und -verfahren

Info

Publication number
ATE174699T1
ATE174699T1 AT95103963T AT95103963T ATE174699T1 AT E174699 T1 ATE174699 T1 AT E174699T1 AT 95103963 T AT95103963 T AT 95103963T AT 95103963 T AT95103963 T AT 95103963T AT E174699 T1 ATE174699 T1 AT E174699T1
Authority
AT
Austria
Prior art keywords
instruction
execution
processing system
dispatch
determination
Prior art date
Application number
AT95103963T
Other languages
English (en)
Inventor
Seungyoon Peter Song
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Application granted granted Critical
Publication of ATE174699T1 publication Critical patent/ATE174699T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G06F9/3863—Recovery, e.g. branch miss-prediction, exception handling using multiple copies of the architectural state, e.g. shadow registers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384—Register renaming
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3856—Reordering of instructions, e.g. using queues or age tags
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Hardware Redundancy (AREA)
  • Retry When Errors Occur (AREA)
  • Preparation Of Compounds By Using Micro-Organisms (AREA)
  • Electrical Discharge Machining, Electrochemical Machining, And Combined Machining (AREA)
  • Executing Machine-Instructions (AREA)
AT95103963T 1994-03-31 1995-03-17 Verarbeitungssystem und -verfahren ATE174699T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/221,438 US5546599A (en) 1994-03-31 1994-03-31 Processing system and method of operation for processing dispatched instructions with detected exceptions

Publications (1)

Publication Number Publication Date
ATE174699T1 true ATE174699T1 (de) 1999-01-15

Family

ID=22827837

Family Applications (1)

Application Number Title Priority Date Filing Date
AT95103963T ATE174699T1 (de) 1994-03-31 1995-03-17 Verarbeitungssystem und -verfahren

Country Status (6)

Country Link
US (1) US5546599A (de)
EP (1) EP0675434B1 (de)
JP (1) JP2694124B2 (de)
KR (1) KR100188502B1 (de)
AT (1) ATE174699T1 (de)
DE (1) DE69506606T2 (de)

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US5692169A (en) * 1990-12-14 1997-11-25 Hewlett Packard Company Method and system for deferring exceptions generated during speculative execution
JP3212213B2 (ja) * 1994-03-16 2001-09-25 株式会社日立製作所 データ処理装置
US5625835A (en) * 1995-05-10 1997-04-29 International Business Machines Corporation Method and apparatus for reordering memory operations in a superscalar or very long instruction word processor
KR100376056B1 (ko) * 1995-12-29 2003-07-22 엘지엔시스(주) 멀티 프로세서 인터럽트 처리장치
US6209083B1 (en) * 1996-02-28 2001-03-27 Via-Cyrix, Inc. Processor having selectable exception handling modes
US5809275A (en) * 1996-03-01 1998-09-15 Hewlett-Packard Company Store-to-load hazard resolution system and method for a processor that executes instructions out of order
US5838942A (en) * 1996-03-01 1998-11-17 Hewlett-Packard Company Panic trap system and method
US5881306A (en) * 1996-12-17 1999-03-09 International Business Machines Corporation Instruction fetch bandwidth analysis
US5838941A (en) * 1996-12-30 1998-11-17 Intel Corporation Out-of-order superscalar microprocessor with a renaming device that maps instructions from memory to registers
US5887185A (en) * 1997-03-19 1999-03-23 Advanced Micro Devices, Inc. Interface for coupling a floating point unit to a reorder buffer
US6098167A (en) * 1997-03-31 2000-08-01 International Business Machines Corporation Apparatus and method for fast unified interrupt recovery and branch recovery in processors supporting out-of-order execution
US5913048A (en) * 1997-03-31 1999-06-15 International Business Machines Corporation Dispatching instructions in a processor supporting out-of-order execution
US5805849A (en) * 1997-03-31 1998-09-08 International Business Machines Corporation Data processing system and method for using an unique identifier to maintain an age relationship between executing instructions
US5870582A (en) * 1997-03-31 1999-02-09 International Business Machines Corporation Method and apparatus for completion of non-interruptible instructions before the instruction is dispatched
US5887161A (en) * 1997-03-31 1999-03-23 International Business Machines Corporation Issuing instructions in a processor supporting out-of-order execution
US5881280A (en) * 1997-07-25 1999-03-09 Hewlett-Packard Company Method and system for selecting instructions for re-execution for in-line exception recovery in a speculative execution processor
US7089404B1 (en) 1999-06-14 2006-08-08 Transmeta Corporation Method and apparatus for enhancing scheduling in an advanced microprocessor
GB2362730B (en) 1999-12-23 2004-02-11 St Microelectronics Sa Computer register watch
GB2365546B (en) * 1999-12-23 2004-02-18 St Microelectronics Sa A computer system with two debug watch modes
US6820190B1 (en) * 2000-02-02 2004-11-16 Hewlett-Packard Development Company, L.P. Method and computer system for decomposing macroinstructions into microinstructions and forcing the parallel issue of at least two microinstructions
US7278011B2 (en) * 2004-04-08 2007-10-02 International Business Machines Corporation Completion table configured to track a larger number of outstanding instructions without increasing the size of the completion table

Family Cites Families (21)

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US5051940A (en) * 1990-04-04 1991-09-24 International Business Machines Corporation Data dependency collapsing hardware apparatus
US5341482A (en) * 1987-03-20 1994-08-23 Digital Equipment Corporation Method for synchronization of arithmetic exceptions in central processing units having pipelined execution units simultaneously executing instructions
JP2858140B2 (ja) * 1988-10-19 1999-02-17 アポロ・コンピューター・インコーポレーテッド パイプラインプロセッサ装置および方法
US5129067A (en) * 1989-06-06 1992-07-07 Advanced Micro Devices, Inc. Multiple instruction decoder for minimizing register port requirements
US5136697A (en) * 1989-06-06 1992-08-04 Advanced Micro Devices, Inc. System for reducing delay for execution subsequent to correctly predicted branch instruction using fetch information stored with each block of instructions in cache
US5077692A (en) * 1990-03-05 1991-12-31 Advanced Micro Devices, Inc. Information storage device with batch select capability
US5261066A (en) * 1990-03-27 1993-11-09 Digital Equipment Corporation Data processing system and method with small fully-associative cache and prefetch buffers
IL94115A (en) * 1990-04-18 1996-06-18 Ibm Israel Dynamic process for creating pseudo-random test templates for pompous hardware design violence
US5214763A (en) * 1990-05-10 1993-05-25 International Business Machines Corporation Digital computer system capable of processing two or more instructions in parallel and having a coche and instruction compounding mechanism
US5197135A (en) * 1990-06-26 1993-03-23 International Business Machines Corporation Memory management for scalable compound instruction set machines with in-memory compounding
CA2045756C (en) * 1990-06-29 1996-08-20 Gregg Bouchard Combined queue for invalidates and return data in multiprocessor system
JPH04172533A (ja) * 1990-11-07 1992-06-19 Toshiba Corp 電子計算機
US5222244A (en) * 1990-12-20 1993-06-22 Intel Corporation Method of modifying a microinstruction with operands specified by an instruction held in an alias register
US5390305A (en) * 1991-03-29 1995-02-14 Kabushiki Kaisha Toshiba Information processing apparatus capable of executing exception at high speed
JP2925818B2 (ja) * 1991-04-05 1999-07-28 株式会社東芝 並列処理制御装置
US5274818A (en) * 1992-02-03 1993-12-28 Thinking Machines Corporation System and method for compiling a fine-grained array based source program onto a course-grained hardware
DE69308548T2 (de) * 1992-05-01 1997-06-12 Seiko Epson Corp Vorrichtung und verfahren zum befehlsabschluss in einem superskalaren prozessor.
US5257216A (en) * 1992-06-10 1993-10-26 Intel Corporation Floating point safe instruction recognition apparatus
US5257214A (en) * 1992-06-16 1993-10-26 Hewlett-Packard Company Qualification of register file write enables using self-timed floating point exception flags
DE69327688T2 (de) * 1992-08-12 2000-09-07 Advanced Micro Devices, Inc. Befehlsdecoder
US5268855A (en) * 1992-09-14 1993-12-07 Hewlett-Packard Company Common format for encoding both single and double precision floating point numbers

Also Published As

Publication number Publication date
EP0675434A3 (de) 1996-08-07
EP0675434B1 (de) 1998-12-16
JP2694124B2 (ja) 1997-12-24
KR950027561A (ko) 1995-10-18
US5546599A (en) 1996-08-13
JPH07271585A (ja) 1995-10-20
KR100188502B1 (ko) 1999-06-01
EP0675434A2 (de) 1995-10-04
DE69506606T2 (de) 1999-07-22
DE69506606D1 (de) 1999-01-28

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Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties