ATE176063T1 - Parallelschlussschnittstellenschaltkreise in rechnersystemen - Google Patents

Parallelschlussschnittstellenschaltkreise in rechnersystemen

Info

Publication number
ATE176063T1
ATE176063T1 AT95301741T AT95301741T ATE176063T1 AT E176063 T1 ATE176063 T1 AT E176063T1 AT 95301741 T AT95301741 T AT 95301741T AT 95301741 T AT95301741 T AT 95301741T AT E176063 T1 ATE176063 T1 AT E176063T1
Authority
AT
Austria
Prior art keywords
control unit
parallel port
data
peripheral device
processor
Prior art date
Application number
AT95301741T
Other languages
English (en)
Inventor
Michael T Wisor
Scott C Johnson
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of ATE176063T1 publication Critical patent/ATE176063T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
    • G06F11/0757—Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0745—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in an input/output transactions management context
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0766—Error or fault reporting or storing
    • G06F11/0772—Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0793—Remedial or corrective actions

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)
  • Communication Control (AREA)
AT95301741T 1994-04-06 1995-03-16 Parallelschlussschnittstellenschaltkreise in rechnersystemen ATE176063T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US22364394A 1994-04-06 1994-04-06

Publications (1)

Publication Number Publication Date
ATE176063T1 true ATE176063T1 (de) 1999-02-15

Family

ID=22837419

Family Applications (1)

Application Number Title Priority Date Filing Date
AT95301741T ATE176063T1 (de) 1994-04-06 1995-03-16 Parallelschlussschnittstellenschaltkreise in rechnersystemen

Country Status (5)

Country Link
US (1) US5666559A (de)
EP (1) EP0676696B1 (de)
JP (1) JP3628372B2 (de)
AT (1) ATE176063T1 (de)
DE (1) DE69507360T2 (de)

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FR2740238B1 (fr) * 1995-10-19 1997-12-05 Sgs Thomson Microelectronics Cellule integrable ddc dediee a un microprocesseur
US5768619A (en) * 1996-02-16 1998-06-16 Advanced Micro Devices, Inc. Method and system for enabling and disabling functions in a peripheral device for a processor system
US6000043A (en) * 1996-06-28 1999-12-07 Intel Corporation Method and apparatus for management of peripheral devices coupled to a bus
US6122256A (en) * 1997-08-18 2000-09-19 International Business Machines Corporation Fail-safe communications network for use in system power control
JP3638769B2 (ja) * 1997-12-01 2005-04-13 株式会社ルネサステクノロジ 通信制御装置
US6085278A (en) * 1998-06-02 2000-07-04 Adaptec, Inc. Communications interface adapter for a computer system including posting of system interrupt status
US6449709B1 (en) 1998-06-02 2002-09-10 Adaptec, Inc. Fast stack save and restore system and method
US6247143B1 (en) * 1998-06-30 2001-06-12 Sun Microsystems, Inc. I/O handling for a multiprocessor computer system
US6189117B1 (en) 1998-08-18 2001-02-13 International Business Machines Corporation Error handling between a processor and a system managed by the processor
US6470463B1 (en) * 1999-03-29 2002-10-22 Inventec Corporation Method and apparatus for testing integrity of data transfer of a hardware
EP1257917A4 (de) * 1999-04-07 2004-11-10 Cradle Technologies Globale bus-synchrone bestätigung einer transaktion mit erkennung des fehlers einer antwort
US6701398B1 (en) 1999-04-07 2004-03-02 Cradle Technologies, Inc. Global bus synchronous transaction acknowledge with nonresponse detection
KR100429267B1 (ko) * 2001-11-27 2004-04-29 엘지전자 주식회사 외부기기 전송 인식 오류 처리장치와 방법
US7200781B2 (en) 2003-05-14 2007-04-03 Hewlett-Packard Development Company, L.P. Detecting and diagnosing a malfunctioning host coupled to a communications bus
US7676621B2 (en) 2003-09-12 2010-03-09 Hewlett-Packard Development Company, L.P. Communications bus transceiver
US7484058B2 (en) * 2004-04-28 2009-01-27 Emc Corporation Reactive deadlock management in storage area networks
WO2005104731A2 (en) * 2004-04-28 2005-11-10 Emc Corporation Reactive deadlock management in storage area networks
US7308617B2 (en) 2004-06-17 2007-12-11 International Business Machines Corporation Apparatus, system, and method for automatically freeing a server resource locked awaiting a failed acknowledgement from a client
TWI311705B (en) * 2005-05-23 2009-07-01 Via Tech Inc Peripheral component interconnect express and changing method of link power states thereof
US7747897B2 (en) * 2005-11-18 2010-06-29 Intel Corporation Method and apparatus for lockstep processing on a fixed-latency interconnect
US7739404B2 (en) * 2006-05-03 2010-06-15 Avaya Inc. Scalable methods for distributing routing information to border gateway protocol (BGP) devices
JP5127927B2 (ja) 2008-08-22 2013-01-23 三菱電機株式会社 バスコントローラ及びバス通信システム及びバス制御方法
RU2434268C2 (ru) * 2009-11-18 2011-11-20 Российская Федерация, от имени которой выступает Министерство промышленности и торговли Российской Федерации (Минпромторг России) Способ сопряжения компьютера с измерительным оборудованием, измерительная система и ограниченный реверсивный счетчик (варианты)
DE102010003538A1 (de) * 2010-03-31 2011-10-06 Robert Bosch Gmbh Verfahren zur Überprüfung von Signal- und Modulaktivitäten in einem Timermodul und Timermodul
JP5582472B2 (ja) * 2010-08-27 2014-09-03 大学共同利用機関法人情報・システム研究機構 Ｌｓｉ演算装置及びその故障検出方法
JP5932146B2 (ja) * 2013-05-20 2016-06-08 華為技術有限公司Ｈｕａｗｅｉ Ｔｅｃｈｎｏｌｏｇｉｅｓ Ｃｏ．，Ｌｔｄ． ピーシーアイエクスプレスのエンドポイントデバイスにアクセスするための方法、コンピューターシステム、および、装置
US9165531B2 (en) 2013-05-27 2015-10-20 Google Technology Holdings LLC System for detecting display driver error when failing to receive a synchronization signal and method thereof
US9843436B2 (en) * 2015-06-27 2017-12-12 Intel Corporation Flexible interconnect architecture

Family Cites Families (8)

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Publication number Priority date Publication date Assignee Title
US4069510A (en) * 1974-10-30 1978-01-17 Motorola, Inc. Interrupt status register for interface adaptor chip
US4159516A (en) * 1976-03-23 1979-06-26 Texas Instruments Incorporated Input/output controller having selectable timing and maskable interrupt generation
US4535404A (en) * 1982-04-29 1985-08-13 Honeywell Information Systems Inc. Method and apparatus for addressing a peripheral interface by mapping into memory address space
JPS60178561A (ja) * 1984-02-24 1985-09-12 Sharp Corp 標準デイジタル・インタ−フエイス装置
US4872110A (en) * 1987-09-03 1989-10-03 Bull Hn Information Systems Inc. Storage of input/output command timeout and acknowledge responses
US5075874A (en) * 1989-04-10 1991-12-24 Eastman Kodak Company Communications interface for computer output printer
US5159684A (en) * 1989-05-24 1992-10-27 Pitney Bowes Inc. Data communication interface integrated circuit with data-echoing and non-echoing communication modes
US5325529A (en) * 1990-05-18 1994-06-28 Compaq Computer Corporation External boot information loading of a personal computer

Also Published As

Publication number Publication date
US5666559A (en) 1997-09-09
EP0676696A1 (de) 1995-10-11
JPH07311716A (ja) 1995-11-28
EP0676696B1 (de) 1999-01-20
DE69507360D1 (de) 1999-03-04
DE69507360T2 (de) 1999-06-17
JP3628372B2 (ja) 2005-03-09

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