ATE180068T1 - Schnelladdierer mit gemischter basis - Google Patents

Schnelladdierer mit gemischter basis

Info

Publication number
ATE180068T1
ATE180068T1 AT91301348T AT91301348T ATE180068T1 AT E180068 T1 ATE180068 T1 AT E180068T1 AT 91301348 T AT91301348 T AT 91301348T AT 91301348 T AT91301348 T AT 91301348T AT E180068 T1 ATE180068 T1 AT E180068T1
Authority
AT
Austria
Prior art keywords
adder
independent
quick
adders
mixed base
Prior art date
Application number
AT91301348T
Other languages
English (en)
Inventor
Thomas W Lynch
Steven D Mcintyre
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of ATE180068T1 publication Critical patent/ATE180068T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G06F7/507—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using selection between two conditionally calculated carry or sum values
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/49—Computations with a radix, other than binary, 8, 16 or decimal, e.g. ternary, negative or imaginary radices, mixed radix non-linear PCM

Landscapes

  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • Complex Calculations (AREA)
  • Pharmaceuticals Containing Other Organic And Inorganic Compounds (AREA)
  • Analogue/Digital Conversion (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Transition And Organic Metals Composition Catalysts For Addition Polymerization (AREA)
  • Lubricants (AREA)
  • Executing Machine-Instructions (AREA)
AT91301348T 1990-04-02 1991-02-20 Schnelladdierer mit gemischter basis ATE180068T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US50381890A 1990-04-02 1990-04-02

Publications (1)

Publication Number Publication Date
ATE180068T1 true ATE180068T1 (de) 1999-05-15

Family

ID=24003637

Family Applications (1)

Application Number Title Priority Date Filing Date
AT91301348T ATE180068T1 (de) 1990-04-02 1991-02-20 Schnelladdierer mit gemischter basis

Country Status (4)

Country Link
EP (1) EP0450752B1 (de)
JP (1) JPH04227533A (de)
AT (1) ATE180068T1 (de)
DE (1) DE69131218D1 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ES2071556B1 (es) * 1992-12-31 1996-01-16 Alcatel Standard Electrica Dispositivo de reduccion del numero de palabras de datos en operaciones aritmeticas binarias.
KR100224278B1 (ko) * 1996-12-18 1999-10-15 윤종용 패스 트랜지스터 로직을 사용하는 조건 합 가산기 및 그것을 구비한 집적 회로
JP2010122741A (ja) * 2008-11-17 2010-06-03 Kumamoto Univ データ処理装置

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3993891A (en) * 1975-07-03 1976-11-23 Burroughs Corporation High speed parallel digital adder employing conditional and look-ahead approaches
JPH01244531A (ja) * 1988-03-25 1989-09-28 Fujitsu Ltd 論理回路

Also Published As

Publication number Publication date
EP0450752B1 (de) 1999-05-12
DE69131218D1 (de) 1999-06-17
EP0450752A2 (de) 1991-10-09
JPH04227533A (ja) 1992-08-17
EP0450752A3 (en) 1993-05-26

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Legal Events

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RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties