ATE181193T1 - Gerät zur erkennung von zellengrenzen in einem bitstrom und crc-generierung - Google Patents

Gerät zur erkennung von zellengrenzen in einem bitstrom und crc-generierung

Info

Publication number
ATE181193T1
ATE181193T1 AT95905101T AT95905101T ATE181193T1 AT E181193 T1 ATE181193 T1 AT E181193T1 AT 95905101 T AT95905101 T AT 95905101T AT 95905101 T AT95905101 T AT 95905101T AT E181193 T1 ATE181193 T1 AT E181193T1
Authority
AT
Austria
Prior art keywords
bit stream
bits
pct
bit
detecting cell
Prior art date
Application number
AT95905101T
Other languages
English (en)
Inventor
Johan Wieant Gerlach Nielander
Franciscus Anna Gerardu Vankan
Original Assignee
Koninkl Kpn Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Kpn Nv filed Critical Koninkl Kpn Nv
Application granted granted Critical
Publication of ATE181193T1 publication Critical patent/ATE181193T1/de

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/048—Speed or phase control by synchronisation signals using the properties of error detecting or error correcting codes, e.g. parity as synchronisation signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0078—Avoidance of errors by organising the transmitted data in a format specifically designed to deal with errors, e.g. location
    • H04L1/0083—Formatting with frames or packets; Protocol or part of protocol for error control
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5672—Multiplexing, e.g. coding, scrambling
    • H04L2012/5674—Synchronisation, timing recovery or alignment

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Error Detection And Correction (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Static Random-Access Memory (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Communication Control (AREA)
  • Color Television Systems (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)
AT95905101T 1993-12-27 1994-12-23 Gerät zur erkennung von zellengrenzen in einem bitstrom und crc-generierung ATE181193T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL9302266A NL9302266A (nl) 1993-12-27 1993-12-27 Inrichting voor het vaststellen van grenzen in een bitstroom, en converteermiddelen voor toepassing in de inrichting.

Publications (1)

Publication Number Publication Date
ATE181193T1 true ATE181193T1 (de) 1999-06-15

Family

ID=19863319

Family Applications (1)

Application Number Title Priority Date Filing Date
AT95905101T ATE181193T1 (de) 1993-12-27 1994-12-23 Gerät zur erkennung von zellengrenzen in einem bitstrom und crc-generierung

Country Status (14)

Country Link
US (1) US5724034A (de)
EP (1) EP0737390B1 (de)
JP (1) JP3002713B2 (de)
KR (1) KR100189267B1 (de)
CN (1) CN1139503A (de)
AT (1) ATE181193T1 (de)
AU (1) AU683712B2 (de)
CA (1) CA2179296C (de)
CZ (1) CZ189296A3 (de)
DE (1) DE69419035T2 (de)
NL (1) NL9302266A (de)
NO (1) NO962729L (de)
PL (1) PL175567B1 (de)
WO (1) WO1995018495A1 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19519946A1 (de) * 1995-06-02 1996-12-05 Thomson Brandt Gmbh Verfahren zur Synchronisation eines aus Informationsdaten und einem anschließenden Prüfsummenfeld bestehenden empfangenen Datenblocks sowie Vorrichtung zur Durchführung des Verfahrens
WO1997041681A1 (en) * 1996-04-26 1997-11-06 Philips Electronics N.V. Magnetic-tape recording/reproducing arrangement comprising a coding device
DE69731932T2 (de) * 1996-10-29 2006-02-16 International Business Machines Corp. Verfahren und Vorrichtung für zweistufige CRC-32-Berechnung
US6928608B2 (en) * 2001-08-14 2005-08-09 Optix Networks Ltd. Apparatus and method for accelerating cyclic redundancy check calculations
JP2003078421A (ja) * 2001-09-04 2003-03-14 Canon Inc 符号系列の先頭位置検出方法とその装置、それを用いた復号方法とその装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4720830A (en) * 1985-12-02 1988-01-19 Advanced Micro Devices, Inc. CRC calculation apparatus having reduced output bus size
JP2816223B2 (ja) * 1990-03-02 1998-10-27 株式会社日立製作所 セル同期回路
JPH04211547A (ja) * 1990-03-20 1992-08-03 Fujitsu Ltd 同期回路
US5131012A (en) * 1990-09-18 1992-07-14 At&T Bell Laboratories Synchronization for cylic redundancy check based, broadband communications network
US5267249A (en) * 1991-05-09 1993-11-30 Codex Corporation Device and method for asynchronous cyclic redundancy checking for digital receivers
JPH07504312A (ja) * 1992-12-29 1995-05-11 コーデックス・コーポレイション 効率的なｃｒｃ剰余係数発生および検査装置および方法
CA2145017C (en) * 1994-03-31 2000-02-15 Masaru Murakami Cell multiplexer having cell delineation function

Also Published As

Publication number Publication date
KR100189267B1 (ko) 1999-06-01
PL175567B1 (pl) 1999-01-29
JPH09500777A (ja) 1997-01-21
DE69419035D1 (de) 1999-07-15
NO962729L (no) 1996-08-21
AU683712B2 (en) 1997-11-20
CA2179296A1 (en) 1995-07-06
NL9302266A (nl) 1995-07-17
CA2179296C (en) 2000-10-17
JP3002713B2 (ja) 2000-01-24
CN1139503A (zh) 1997-01-01
EP0737390B1 (de) 1999-06-09
EP0737390A1 (de) 1996-10-16
CZ189296A3 (en) 1996-11-13
WO1995018495A1 (en) 1995-07-06
NO962729D0 (no) 1996-06-27
AU1384895A (en) 1995-07-17
DE69419035T2 (de) 2000-01-27
US5724034A (en) 1998-03-03
PL315146A1 (en) 1996-10-14

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Legal Events

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