ATE189070T1 - Zwischenverbindungssystem für multiprozessorstruktur - Google Patents

Zwischenverbindungssystem für multiprozessorstruktur

Info

Publication number
ATE189070T1
ATE189070T1 AT88311138T AT88311138T ATE189070T1 AT E189070 T1 ATE189070 T1 AT E189070T1 AT 88311138 T AT88311138 T AT 88311138T AT 88311138 T AT88311138 T AT 88311138T AT E189070 T1 ATE189070 T1 AT E189070T1
Authority
AT
Austria
Prior art keywords
transfer
cells
stages
another
stage
Prior art date
Application number
AT88311138T
Other languages
English (en)
Inventor
Steven J Frank
Henry Burkhardt Iii
Frederick D Weber
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Application granted granted Critical
Publication of ATE189070T1 publication Critical patent/ATE189070T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17337—Direct connection machines, e.g. completely connected computers, point to point communication networks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/42—Loop networks
    • H04L12/427—Loop networks with decentralised control
    • H04L12/433—Loop networks with decentralised control with asynchronous transmission, e.g. token ring, register insertion

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Mathematical Physics (AREA)
  • Signal Processing (AREA)
  • Multi Processors (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Bus Control (AREA)
  • Steering Control In Accordance With Driving Conditions (AREA)
  • Hardware Redundancy (AREA)
  • Complex Calculations (AREA)
AT88311138T 1987-12-22 1988-11-24 Zwischenverbindungssystem für multiprozessorstruktur ATE189070T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13670187A 1987-12-22 1987-12-22

Publications (1)

Publication Number Publication Date
ATE189070T1 true ATE189070T1 (de) 2000-02-15

Family

ID=22473982

Family Applications (1)

Application Number Title Priority Date Filing Date
AT88311138T ATE189070T1 (de) 1987-12-22 1988-11-24 Zwischenverbindungssystem für multiprozessorstruktur

Country Status (5)

Country Link
EP (2) EP0936778A1 (de)
JP (1) JP2782521B2 (de)
AT (1) ATE189070T1 (de)
CA (1) CA1320003C (de)
DE (1) DE3856394T2 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5761413A (en) * 1987-12-22 1998-06-02 Sun Microsystems, Inc. Fault containment system for multiprocessor with shared memory
CA2019300C (en) 1989-06-22 2001-06-12 Kendall Square Research Corporation Multiprocessor system with shared memory
CA2078315A1 (en) * 1991-09-20 1993-03-21 Christopher L. Reeve Parallel processing apparatus and method for utilizing tiling
CA2078312A1 (en) 1991-09-20 1993-03-21 Mark A. Kaufman Digital data processor with improved paging
DE19816153B4 (de) * 1997-05-01 2005-06-23 Hewlett-Packard Development Co., L.P., Houston Busverbindungssystem
US6115756A (en) * 1997-06-27 2000-09-05 Sun Microsystems, Inc. Electro-optically connected multiprocessor and multiring configuration for dynamically allocating time
JP4934356B2 (ja) * 2006-06-20 2012-05-16 株式会社日立製作所 映像処理エンジンおよびそれを含む映像処理システム
DE102008004857B4 (de) 2008-01-17 2013-08-22 Entropic Communications, Inc. Verfahren zur Übertragung von Daten zwischen wenigstens zwei Taktdomänen
JP7131115B2 (ja) * 2018-06-21 2022-09-06 日本電気株式会社 データ処理装置、データ処理方法、およびプログラム

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1580057A (en) * 1976-07-16 1980-11-26 Post Office Information handling apparatus
IT1118355B (it) * 1979-02-15 1986-02-24 Cselt Centro Studi Lab Telecom Sistema di interconnessione tra processori
GB2077468B (en) * 1980-06-04 1984-10-24 Hitachi Ltd Multi-computer system with plural serial bus loops
JPS57166756A (en) * 1981-04-08 1982-10-14 Hitachi Ltd Transmission controlling method
US4663706A (en) * 1982-10-28 1987-05-05 Tandem Computers Incorporated Multiprocessor multisystem communications network
JPS59103166A (ja) * 1982-12-02 1984-06-14 Fujitsu Ltd 階層型並列デ−タ処理装置
US4622631B1 (en) * 1983-12-30 1996-04-09 Recognition Int Inc Data processing system having a data coherence solution

Also Published As

Publication number Publication date
EP0322116A2 (de) 1989-06-28
EP0322116B1 (de) 2000-01-19
DE3856394D1 (de) 2000-02-24
EP0322116A3 (de) 1990-08-08
CA1320003C (en) 1993-07-06
DE3856394T2 (de) 2000-05-18
JP2782521B2 (ja) 1998-08-06
EP0936778A1 (de) 1999-08-18
JPH022451A (ja) 1990-01-08

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Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties