ATE195594T1 - System zur dynamischen zuordnung von speicher registern zum herstellen von pseudowarteschlangen - Google Patents

System zur dynamischen zuordnung von speicher registern zum herstellen von pseudowarteschlangen

Info

Publication number
ATE195594T1
ATE195594T1 AT94906690T AT94906690T ATE195594T1 AT E195594 T1 ATE195594 T1 AT E195594T1 AT 94906690 T AT94906690 T AT 94906690T AT 94906690 T AT94906690 T AT 94906690T AT E195594 T1 ATE195594 T1 AT E195594T1
Authority
AT
Austria
Prior art keywords
queue
task
register
registers
header
Prior art date
Application number
AT94906690T
Other languages
English (en)
Inventor
Stephen R Cornaby
Original Assignee
Seagate Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seagate Technology filed Critical Seagate Technology
Application granted granted Critical
Publication of ATE195594T1 publication Critical patent/ATE195594T1/de

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/76Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
    • G06F7/78Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data for changing the order of data flow, e.g. matrix transposition or LIFO buffers; Overflow or underflow handling therefor
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2205/00Indexing scheme relating to group G06F5/00; Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F2205/06Indexing scheme relating to groups G06F5/06 - G06F5/16
    • G06F2205/064Linked list, i.e. structure using pointers, e.g. allowing non-contiguous address segments in one logical buffer or dynamic buffer space allocation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Multi Processors (AREA)
  • Exchange Systems With Centralized Control (AREA)
AT94906690T 1993-01-21 1994-01-18 System zur dynamischen zuordnung von speicher registern zum herstellen von pseudowarteschlangen ATE195594T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/007,199 US5410722A (en) 1993-01-21 1993-01-21 Queue system for dynamically allocating and moving memory registers between a plurality of pseudo queues
PCT/US1994/000699 WO1994017470A1 (en) 1993-01-21 1994-01-18 System for dynamically allocating memory registers for forming pseudo queues

Publications (1)

Publication Number Publication Date
ATE195594T1 true ATE195594T1 (de) 2000-09-15

Family

ID=21724778

Family Applications (1)

Application Number Title Priority Date Filing Date
AT94906690T ATE195594T1 (de) 1993-01-21 1994-01-18 System zur dynamischen zuordnung von speicher registern zum herstellen von pseudowarteschlangen

Country Status (6)

Country Link
US (1) US5410722A (de)
EP (1) EP0680633B1 (de)
JP (1) JP3271981B2 (de)
AT (1) ATE195594T1 (de)
DE (1) DE69425554T2 (de)
WO (1) WO1994017470A1 (de)

Families Citing this family (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6067613A (en) * 1993-11-30 2000-05-23 Texas Instruments Incorporated Rotation register for orthogonal data transformation
GB9600336D0 (en) * 1996-01-09 1996-03-13 Int Computers Ltd Arbitration method and apparatus
US5872938A (en) * 1996-06-28 1999-02-16 International Business Machines Corp. Service priority queue implemented with ordered sub-queues and sub-queue pointers pointing to last entries in respective sub-queues
US5949994A (en) * 1997-02-12 1999-09-07 The Dow Chemical Company Dedicated context-cycling computer with timed context
US6119196A (en) * 1997-06-30 2000-09-12 Sun Microsystems, Inc. System having multiple arbitrating levels for arbitrating access to a shared memory by network ports operating at different data rates
US6014380A (en) * 1997-06-30 2000-01-11 Sun Microsystems, Inc. Mechanism for packet field replacement in a multi-layer distributed network element
US6246680B1 (en) 1997-06-30 2001-06-12 Sun Microsystems, Inc. Highly integrated multi-layer switch element architecture
US6044087A (en) * 1997-06-30 2000-03-28 Sun Microsystems, Inc. Interface for a highly integrated ethernet network element
US6052738A (en) * 1997-06-30 2000-04-18 Sun Microsystems, Inc. Method and apparatus in a packet routing switch for controlling access at different data rates to a shared memory
US6128666A (en) * 1997-06-30 2000-10-03 Sun Microsystems, Inc. Distributed VLAN mechanism for packet field replacement in a multi-layered switched network element using a control field/signal for indicating modification of a packet with a database search engine
US6088356A (en) * 1997-06-30 2000-07-11 Sun Microsystems, Inc. System and method for a multi-layer network element
US6081512A (en) * 1997-06-30 2000-06-27 Sun Microsystems, Inc. Spanning tree support in a high performance network device
US6049528A (en) * 1997-06-30 2000-04-11 Sun Microsystems, Inc. Trunking ethernet-compatible networks
US6094435A (en) * 1997-06-30 2000-07-25 Sun Microsystems, Inc. System and method for a quality of service in a multi-layer network element
US6081522A (en) * 1997-06-30 2000-06-27 Sun Microsystems, Inc. System and method for a multi-layer network element
US6044418A (en) * 1997-06-30 2000-03-28 Sun Microsystems, Inc. Method and apparatus for dynamically resizing queues utilizing programmable partition pointers
US6016310A (en) * 1997-06-30 2000-01-18 Sun Microsystems, Inc. Trunking support in a high performance network device
US5938736A (en) * 1997-06-30 1999-08-17 Sun Microsystems, Inc. Search engine architecture for a high performance multi-layer switch element
US5920566A (en) * 1997-06-30 1999-07-06 Sun Microsystems, Inc. Routing in a multi-layer distributed network element
US6308167B1 (en) * 1998-04-09 2001-10-23 Compaq Computer Corporation Computer system using a queuing system and method for managing a queue and heterogeneous data structures
US6842899B2 (en) 1999-12-21 2005-01-11 Lockheed Martin Corporation Apparatus and method for resource negotiations among autonomous agents
US6892250B2 (en) * 2000-02-09 2005-05-10 Seagate Technology Llc Command queue processor
US6823351B1 (en) * 2000-05-15 2004-11-23 Sun Microsystems, Inc. Work-stealing queues for parallel garbage collection
US7103887B2 (en) * 2001-06-27 2006-09-05 Sun Microsystems, Inc. Load-balancing queues employing LIFO/FIFO work stealing
US6845444B2 (en) * 2001-08-23 2005-01-18 Silicon Integrated Systems Corp. Method and apparatus for reducing strapping devices
US6987761B2 (en) 2002-02-13 2006-01-17 International Business Machines Corporation Inbound data stream controller with pre-recognition of frame sequence
US20070074013A1 (en) * 2003-08-25 2007-03-29 Lonnie Goff Dynamic retention of hardware register content in a computer system
US8776049B2 (en) 2004-10-20 2014-07-08 Seagate Technology Llc Address aligned resource set allocation in a memory space
CN101796487B (zh) 2007-08-10 2013-10-09 科尼龙硅公司 虚拟队列处理电路以及任务处理器
US7971041B2 (en) * 2008-05-29 2011-06-28 Advanced Micro Devices, Inc. Method and system for register management
US8904003B2 (en) * 2008-06-30 2014-12-02 Oracle America, Inc. Method and system for delegated job control across a network
US10157060B2 (en) 2011-12-29 2018-12-18 Intel Corporation Method, device and system for control signaling in a data path module of a data stream processing engine
US10331583B2 (en) 2013-09-26 2019-06-25 Intel Corporation Executing distributed memory operations using processing elements connected by distributed channels
US9536010B2 (en) * 2014-08-11 2017-01-03 Amadeus S.A.S. Automated ticketing
US11086816B2 (en) 2017-09-28 2021-08-10 Intel Corporation Processors, methods, and systems for debugging a configurable spatial accelerator
US11307873B2 (en) 2018-04-03 2022-04-19 Intel Corporation Apparatus, methods, and systems for unstructured data flow in a configurable spatial accelerator with predicate propagation and merging
US10891240B2 (en) 2018-06-30 2021-01-12 Intel Corporation Apparatus, methods, and systems for low latency communication in a configurable spatial accelerator
US11200186B2 (en) 2018-06-30 2021-12-14 Intel Corporation Apparatuses, methods, and systems for operations in a configurable spatial accelerator
US10853073B2 (en) 2018-06-30 2020-12-01 Intel Corporation Apparatuses, methods, and systems for conditional operations in a configurable spatial accelerator
US10915471B2 (en) 2019-03-30 2021-02-09 Intel Corporation Apparatuses, methods, and systems for memory interface circuit allocation in a configurable spatial accelerator
US10817291B2 (en) 2019-03-30 2020-10-27 Intel Corporation Apparatuses, methods, and systems for swizzle operations in a configurable spatial accelerator
US11037050B2 (en) 2019-06-29 2021-06-15 Intel Corporation Apparatuses, methods, and systems for memory interface circuit arbitration in a configurable spatial accelerator
US12086080B2 (en) 2020-09-26 2024-09-10 Intel Corporation Apparatuses, methods, and systems for a configurable accelerator having dataflow execution circuits

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4646231A (en) * 1983-07-21 1987-02-24 Burroughs Corporation Method of synchronizing the sequence by which a variety of randomly called unrelated activities are executed in a digital processor
US5010482A (en) * 1987-07-02 1991-04-23 Unisys Corp. Multi-event mechanism for queuing happened events for a large data processing system
JPH02178730A (ja) * 1988-12-28 1990-07-11 Toshiba Corp 分割法を用いた内部ソート方式
US5093912A (en) * 1989-06-26 1992-03-03 International Business Machines Corporation Dynamic resource pool expansion and contraction in multiprocessing environments
US5129084A (en) * 1989-06-29 1992-07-07 Digital Equipment Corporation Object container transfer system and method in an object based computer operating system
US5263160A (en) * 1991-01-31 1993-11-16 Digital Equipment Corporation Augmented doubly-linked list search and management method for a system having data stored in a list of data elements in memory

Also Published As

Publication number Publication date
EP0680633A1 (de) 1995-11-08
DE69425554D1 (de) 2000-09-21
EP0680633B1 (de) 2000-08-16
EP0680633A4 (de) 1996-03-13
WO1994017470A1 (en) 1994-08-04
US5410722A (en) 1995-04-25
DE69425554T2 (de) 2001-01-04
JP3271981B2 (ja) 2002-04-08
JPH08506197A (ja) 1996-07-02

Similar Documents

Publication Publication Date Title
ATE195594T1 (de) System zur dynamischen zuordnung von speicher registern zum herstellen von pseudowarteschlangen
KR940015852A (ko) 긴 명령 워드를 갖는 처리기
KR940018757A (ko) 슈퍼스칼라 프로페서 시스템에서 중간 기억 버퍼의 할당을 인덱스하기 위한 방법 및 시스템
TW486666B (en) Register set used in multithreaded parallel processor architecture
ATE253238T1 (de) Parallele prozessorarchitektur
TW335466B (en) Data processor and shade processor
DE60009102D1 (de) Sdram-steuerungvorrichtung für parallele prozessorarchitektur
ES467326A1 (es) Un controlador de linea general de canales en un sistema de tratamiento de datos.
EP0735463A3 (de) Rechnerprozessor mit Registerspeicher mit reduzierter Bandbreite von Lese- und/oder Schreibtor
KR960700475A (ko) 명령어 실행 제어를 위해 명령어에 태그를 할당하는 시스템 및 방법
KR940022250A (ko) 가장 최근에 할당된 비트를 갖는 데이타 프로세서 및 그 동작 방법
ES488841A1 (es) Un sistema perfeccionado de tratamiento de datos.
ES398425A1 (es) Una unidad de almacenamiento para senales representativas de (paginas) de datos y sus direcciones.
DE59910781D1 (de) Verteiles steuerungssystem mit lagebestimmung der komponenten
KR850002907A (ko) Cpu 마이크로 분기구조
DE69807412D1 (de) Prozessorarchitekturschema und Befehlssatz zur Maximierung verfügbarer Opcodes und zum Einsetzen verschiedener Adressierungsmodi
KR900005296A (ko) 버퍼 기억장치 시스템
CA2377765A1 (en) Data processors
DE50005539D1 (de) Tragbarer datenträger und verfahren zur nutzung in einer mehrzahl von anwendungen
KR940017887A (ko) 동화상 복호 장치
TW267222B (en) Improved method and system of addressing
RU94024078A (ru) Параллельный процессор с перепрограммируемой структурой
JPS63142434A (ja) 割込み制御方式
JPS6461822A (en) Register allocation system
ES1022407U (es) Captadioptrico de uso personal.

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties