ATE198680T1 - Verfahren zur herstellung einer halbleiteranordnung mit einem bipolartransistor - Google Patents
Verfahren zur herstellung einer halbleiteranordnung mit einem bipolartransistorInfo
- Publication number
- ATE198680T1 ATE198680T1 AT91304968T AT91304968T ATE198680T1 AT E198680 T1 ATE198680 T1 AT E198680T1 AT 91304968 T AT91304968 T AT 91304968T AT 91304968 T AT91304968 T AT 91304968T AT E198680 T1 ATE198680 T1 AT E198680T1
- Authority
- AT
- Austria
- Prior art keywords
- region
- semiconductor
- semiconductor device
- bipolar transistor
- semiconductor region
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/012—Manufacture or treatment of static induction transistors [SIT], e.g. permeable base transistors [PBT]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/40—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
- H10D84/401—Combinations of FETs or IGBTs with BJTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D10/00—Bipolar junction transistors [BJT]
- H10D10/01—Manufacture or treatment
- H10D10/051—Manufacture or treatment of vertical BJTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
- H10D62/137—Collector regions of BJTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
- H10D64/231—Emitter or collector electrodes for bipolar transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0107—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs
- H10D84/0109—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs the at least one component covered by H10D12/00 or H10D30/00 being a MOS device
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/24—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using chemical vapour deposition [CVD]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/01—Manufacture or treatment
- H10W10/031—Manufacture or treatment of isolation regions comprising PN junctions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/30—Isolation regions comprising PN junctions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
Landscapes
- Electrodes Of Semiconductors (AREA)
- Bipolar Transistors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Thin Film Transistor (AREA)
- Die Bonding (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13962290 | 1990-05-31 | ||
| JP31159390 | 1990-11-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ATE198680T1 true ATE198680T1 (de) | 2001-01-15 |
Family
ID=26472369
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AT91304968T ATE198680T1 (de) | 1990-05-31 | 1991-05-31 | Verfahren zur herstellung einer halbleiteranordnung mit einem bipolartransistor |
Country Status (8)
| Country | Link |
|---|---|
| US (2) | US5306934A (de) |
| EP (1) | EP0462717B1 (de) |
| KR (1) | KR950010283B1 (de) |
| CN (1) | CN1035850C (de) |
| AT (1) | ATE198680T1 (de) |
| DE (1) | DE69132505T2 (de) |
| MY (1) | MY107443A (de) |
| SG (1) | SG43260A1 (de) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5559044A (en) * | 1992-09-21 | 1996-09-24 | Siliconix Incorporated | BiCDMOS process technology |
| JP2001085463A (ja) * | 1999-09-09 | 2001-03-30 | Rohm Co Ltd | 半導体チップおよびそれを用いた半導体装置 |
| US6703707B1 (en) * | 1999-11-24 | 2004-03-09 | Denso Corporation | Semiconductor device having radiation structure |
| JP2003017498A (ja) * | 2001-07-02 | 2003-01-17 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
| US6815801B2 (en) * | 2003-02-28 | 2004-11-09 | Texas Instrument Incorporated | Vertical bipolar transistor and a method of manufacture therefor including two epitaxial layers and a buried layer |
| JP5048242B2 (ja) * | 2005-11-30 | 2012-10-17 | オンセミコンダクター・トレーディング・リミテッド | 半導体装置及びその製造方法 |
| US20120098142A1 (en) * | 2010-10-26 | 2012-04-26 | Stmicroelectronics S.R.L. | Electrical contact for a deep buried layer in a semi-conductor device |
| US9722041B2 (en) | 2012-09-19 | 2017-08-01 | Vishay-Siliconix | Breakdown voltage blocking device |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1534896A (en) * | 1975-05-19 | 1978-12-06 | Itt | Direct metal contact to buried layer |
| GB2038883B (en) * | 1978-11-09 | 1982-12-08 | Standard Telephones Cables Ltd | Metallizing semiconductor devices |
| CN1004456B (zh) * | 1985-04-19 | 1989-06-07 | 三洋电机株式会社 | 半导体器件及其制造方法 |
| JP2542676B2 (ja) * | 1987-07-02 | 1996-10-09 | 株式会社東芝 | ヘテロ接合バイポ―ラトランジスタ |
| EP0306213A3 (de) * | 1987-09-02 | 1990-05-30 | AT&T Corp. | Submikron-Bipolartransistor mit seitlichen Kontakten |
| US5270224A (en) * | 1988-03-11 | 1993-12-14 | Fujitsu Limited | Method of manufacturing a semiconductor device having a region doped to a level exceeding the solubility limit |
| US5213999A (en) * | 1990-09-04 | 1993-05-25 | Delco Electronics Corporation | Method of metal filled trench buried contacts |
-
1991
- 1991-05-30 KR KR1019910008917A patent/KR950010283B1/ko not_active Expired - Fee Related
- 1991-05-31 SG SG1996006616A patent/SG43260A1/en unknown
- 1991-05-31 CN CN91103964A patent/CN1035850C/zh not_active Expired - Fee Related
- 1991-05-31 MY MYPI91000961A patent/MY107443A/en unknown
- 1991-05-31 AT AT91304968T patent/ATE198680T1/de active
- 1991-05-31 EP EP91304968A patent/EP0462717B1/de not_active Expired - Lifetime
- 1991-05-31 DE DE69132505T patent/DE69132505T2/de not_active Expired - Fee Related
-
1992
- 1992-01-17 US US07/823,604 patent/US5306934A/en not_active Expired - Fee Related
-
1993
- 1993-10-01 US US08/130,461 patent/US5364802A/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| DE69132505D1 (de) | 2001-02-15 |
| EP0462717A2 (de) | 1991-12-27 |
| US5364802A (en) | 1994-11-15 |
| SG43260A1 (en) | 1997-10-17 |
| EP0462717A3 (en) | 1992-04-08 |
| MY107443A (en) | 1995-12-30 |
| KR910020886A (ko) | 1991-12-20 |
| DE69132505T2 (de) | 2001-06-28 |
| CN1035850C (zh) | 1997-09-10 |
| CN1059234A (zh) | 1992-03-04 |
| US5306934A (en) | 1994-04-26 |
| EP0462717B1 (de) | 2001-01-10 |
| KR950010283B1 (ko) | 1995-09-12 |
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