ATE203851T1 - Verfahren und vorrichtung zum zugriff auf inneren prüfschaltungen in einer integrierten schaltung - Google Patents

Verfahren und vorrichtung zum zugriff auf inneren prüfschaltungen in einer integrierten schaltung

Info

Publication number
ATE203851T1
ATE203851T1 AT97943405T AT97943405T ATE203851T1 AT E203851 T1 ATE203851 T1 AT E203851T1 AT 97943405 T AT97943405 T AT 97943405T AT 97943405 T AT97943405 T AT 97943405T AT E203851 T1 ATE203851 T1 AT E203851T1
Authority
AT
Austria
Prior art keywords
circuit
integrated circuit
test
externally accessible
test circuit
Prior art date
Application number
AT97943405T
Other languages
English (en)
Inventor
Gordon Roberts
James E Miler Jr
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Application granted granted Critical
Publication of ATE203851T1 publication Critical patent/ATE203851T1/de

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/273—Tester hardware, i.e. output processing circuits
    • G06F11/2733—Test interface between tester and unit under test
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2273—Test methods

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Dram (AREA)
AT97943405T 1996-09-20 1997-09-18 Verfahren und vorrichtung zum zugriff auf inneren prüfschaltungen in einer integrierten schaltung ATE203851T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/717,133 US5734661A (en) 1996-09-20 1996-09-20 Method and apparatus for providing external access to internal integrated circuit test circuits
PCT/US1997/016724 WO1998012707A1 (en) 1996-09-20 1997-09-18 Method and apparatus for providing external access to internal integrated circuit test circuits

Publications (1)

Publication Number Publication Date
ATE203851T1 true ATE203851T1 (de) 2001-08-15

Family

ID=24880837

Family Applications (1)

Application Number Title Priority Date Filing Date
AT97943405T ATE203851T1 (de) 1996-09-20 1997-09-18 Verfahren und vorrichtung zum zugriff auf inneren prüfschaltungen in einer integrierten schaltung

Country Status (8)

Country Link
US (1) US5734661A (de)
EP (1) EP0927422B1 (de)
JP (1) JP3696890B2 (de)
KR (1) KR100458344B1 (de)
AT (1) ATE203851T1 (de)
AU (1) AU4488797A (de)
DE (1) DE69705955T2 (de)
WO (1) WO1998012707A1 (de)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6694465B1 (en) * 1994-12-16 2004-02-17 Texas Instruments Incorporated Low overhead input and output boundary scan cells
US5936900A (en) * 1996-12-19 1999-08-10 Texas Instruments Incorporated Integrated circuit memory device having built-in self test circuit with monitor and tester modes
TW384477B (en) * 1997-06-23 2000-03-11 Samsung Electronics Co Ltd Merged memory logic semiconductor device, memory test control circuit and memory test method
US5944845A (en) * 1997-06-26 1999-08-31 Micron Technology, Inc. Circuit and method to prevent inadvertent test mode entry
US6216240B1 (en) 1997-06-26 2001-04-10 Samsung Electronics Co., Ltd. Merged memory and logic (MML) integrated circuits including memory test controlling circuits and methods
JP3866444B2 (ja) * 1998-04-22 2007-01-10 東芝マイクロエレクトロニクス株式会社 半導体装置及びその内部信号モニタ方法
KR100307626B1 (ko) 1998-08-31 2001-11-30 윤종용 디램과버퍼메모리를갖는메모리로직복합집적회로장치
US6266787B1 (en) * 1998-10-09 2001-07-24 Agilent Technologies, Inc. Method and apparatus for selecting stimulus locations during limited access circuit test
KR100688480B1 (ko) * 2000-09-19 2007-03-08 삼성전자주식회사 패키지 상태에서의 반도체 소자의 전기적 특성 측정 수단및 그 방법
ITRM20010556A1 (it) * 2001-09-12 2003-03-12 Micron Technology Inc Decodificatore per decodificare i comandi di commutazione a modo di test di circuiti integrati.
JP2003168300A (ja) * 2001-11-29 2003-06-13 Mitsubishi Electric Corp 半導体装置
US6944812B2 (en) * 2002-01-15 2005-09-13 Micron Technology, Inc. Mode entry circuit and method
US6898750B2 (en) * 2002-01-16 2005-05-24 Microtune (San Diego), Inc. In-chip monitoring system to monitor input/output of functional blocks
JP4313544B2 (ja) * 2002-05-15 2009-08-12 富士通マイクロエレクトロニクス株式会社 半導体集積回路
US6967348B2 (en) * 2002-06-20 2005-11-22 Micron Technology, Inc. Signal sharing circuit with microelectric die isolation features
US7026646B2 (en) * 2002-06-20 2006-04-11 Micron Technology, Inc. Isolation circuit
JP2007500356A (ja) * 2003-05-28 2007-01-11 コーニンクレッカ　フィリップス　エレクトロニクス　エヌ　ヴィ シグナルインテグリティ自己テストアーキテクチャ
DE102004057819B4 (de) * 2004-12-01 2010-07-22 Qimonda Ag Eingangsschaltung für eine integrierte Schaltung
US7583087B2 (en) * 2005-02-22 2009-09-01 Integrated Device Technology, Inc. In-situ monitor of process and device parameters in integrated circuits
US7594149B2 (en) * 2005-02-22 2009-09-22 Integrated Device Technology, Inc. In-situ monitor of process and device parameters in integrated circuits
US20070263472A1 (en) * 2006-05-11 2007-11-15 Anderson Brent A Process environment variation evaluation
US7966530B2 (en) * 2007-12-18 2011-06-21 Micron Technology, Inc. Methods, devices, and systems for experiencing reduced unequal testing degradation
US8779790B2 (en) * 2009-06-26 2014-07-15 Freescale Semiconductor, Inc. Probing structure for evaluation of slow slew-rate square wave signals in low power circuits
CN102708014B (zh) * 2012-05-14 2015-06-24 江苏中科梦兰电子科技有限公司 支持笔记本超低温工作的双嵌入式控制器电路和控制方法
US9500700B1 (en) * 2013-11-15 2016-11-22 Xilinx, Inc. Circuits for and methods of testing the operation of an input/output port
US11144104B2 (en) * 2020-02-14 2021-10-12 Silicon Laboratories Inc. Mode selection circuit for low-cost integrated circuits such as microcontrollers

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5535331A (en) * 1987-09-04 1996-07-09 Texas Instruments Incorporated Processor condition sensing circuits, systems and methods
IL96808A (en) * 1990-04-18 1996-03-31 Rambus Inc Introductory / Origin Circuit Agreed Using High-Performance Brokerage
US5245577A (en) * 1990-11-06 1993-09-14 Micron Technology, Inc. Integrated circuit two-cycle test mode activation circuit
JP3377225B2 (ja) * 1992-04-07 2003-02-17 富士写真フイルム株式会社 チェック回路を含む集積回路
US5508631A (en) * 1994-10-27 1996-04-16 Mitel Corporation Semiconductor test chip with on wafer switching matrix

Also Published As

Publication number Publication date
US5734661A (en) 1998-03-31
AU4488797A (en) 1998-04-14
KR100458344B1 (ko) 2004-11-26
DE69705955T2 (de) 2002-04-04
JP3696890B2 (ja) 2005-09-21
EP0927422B1 (de) 2001-08-01
KR20000048507A (ko) 2000-07-25
JP2002516015A (ja) 2002-05-28
WO1998012707A1 (en) 1998-03-26
EP0927422A1 (de) 1999-07-07
DE69705955D1 (de) 2001-09-06

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Legal Events

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