Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C8/00—Arrangements for selecting an address in a digital store
  • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F13/38—Information transfer, e.g. on bus
  • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
  • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
  • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
  • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
  • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
  • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
  • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
  • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Landscapes

• Engineering & Computer Science (AREA)
• Theoretical Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Physics & Mathematics (AREA)
• General Engineering & Computer Science (AREA)
• General Physics & Mathematics (AREA)
• Memory System Of A Hierarchy Structure (AREA)
• Static Random-Access Memory (AREA)
• Non-Volatile Memory (AREA)
• Information Transfer Systems (AREA)

Applications Claiming Priority (1)

Publications (1)

Family

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Family Applications (1)

Country Status (5)

Families Citing this family (18)

Family Cites Families (6)

• 1993
  • 1993-03-22 US US08/034,288 patent/US5604884A/en not_active Expired - Lifetime
• 1994
  • 1994-03-16 CA CA002119200A patent/CA2119200C/en not_active Expired - Fee Related
  • 1994-03-21 DE DE69428071T patent/DE69428071T2/de not_active Expired - Fee Related
  • 1994-03-21 EP EP94301988A patent/EP0621539B1/de not_active Expired - Lifetime
  • 1994-03-21 AT AT94301988T patent/ATE204996T1/de active
• 1997
  • 1997-02-14 US US08/801,738 patent/US5809549A/en not_active Expired - Lifetime

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