ATE205039T1 - Einzelpaketmeldung in einer datenverbindungssteuereinrichtung - Google Patents

Einzelpaketmeldung in einer datenverbindungssteuereinrichtung

Info

Publication number
ATE205039T1
ATE205039T1 AT94118106T AT94118106T ATE205039T1 AT E205039 T1 ATE205039 T1 AT E205039T1 AT 94118106 T AT94118106 T AT 94118106T AT 94118106 T AT94118106 T AT 94118106T AT E205039 T1 ATE205039 T1 AT E205039T1
Authority
AT
Austria
Prior art keywords
monitoring
character
characters
receive
transmit
Prior art date
Application number
AT94118106T
Other languages
English (en)
Inventor
Dale E Gulick
Terry G Lawell
Charles Crowe
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of ATE205039T1 publication Critical patent/ATE205039T1/de

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/901—Buffering arrangements using storage descriptor, e.g. read or write pointers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9031—Wraparound memory, e.g. overrun or underrun detection
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9063—Intermediate storage in different physical parts of a node or terminal
    • H04L49/9068—Intermediate storage in different physical parts of a node or terminal in the network interface card
    • H04L49/9073—Early interruption upon arrival of a fraction of a packet
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9063—Intermediate storage in different physical parts of a node or terminal
    • H04L49/9078—Intermediate storage in different physical parts of a node or terminal using an external memory or storage device
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/40—Network security protocols
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computer Security & Cryptography (AREA)
  • Communication Control (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Computer And Data Communications (AREA)
  • Selective Calling Equipment (AREA)
AT94118106T 1987-04-03 1988-03-25 Einzelpaketmeldung in einer datenverbindungssteuereinrichtung ATE205039T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/035,817 US4852088A (en) 1987-04-03 1987-04-03 Packet-at-a-time reporting in a data link controller

Publications (1)

Publication Number Publication Date
ATE205039T1 true ATE205039T1 (de) 2001-09-15

Family

ID=21884945

Family Applications (1)

Application Number Title Priority Date Filing Date
AT94118106T ATE205039T1 (de) 1987-04-03 1988-03-25 Einzelpaketmeldung in einer datenverbindungssteuereinrichtung

Country Status (5)

Country Link
US (1) US4852088A (de)
EP (2) EP0290129A3 (de)
JP (1) JP2719522B2 (de)
AT (1) ATE205039T1 (de)
DE (1) DE3856486T2 (de)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0285330A3 (de) * 1987-04-03 1989-09-06 Advanced Micro Devices, Inc. Daten-Protokoll-Steuerung
IT1237301B (it) * 1989-11-30 1993-05-27 Marco Gandini Interfaccia di protocollo multimedia per flusso dati a 64 kbit/s.
JPH04162856A (ja) * 1990-10-26 1992-06-08 Nec Corp エラー表示方式
US5301186A (en) * 1991-06-28 1994-04-05 Digital Equipment Corporation High speed transmission line interface
US5377184A (en) * 1992-03-02 1994-12-27 International Business Machines Corporation Method of controlling TWA link in a communications adapter by monitoring buffer fill levels
US5412782A (en) * 1992-07-02 1995-05-02 3Com Corporation Programmed I/O ethernet adapter with early interrupts for accelerating data transfer
US5307459A (en) * 1992-07-28 1994-04-26 3Com Corporation Network adapter with host indication optimization
US5434872A (en) * 1992-07-28 1995-07-18 3Com Corporation Apparatus for automatic initiation of data transmission
US5574848A (en) * 1993-08-24 1996-11-12 National Semiconductor Corporation Can interface selecting one of two distinct fault recovery method after counting a predetermined number of recessive bits or good can frames
US5548796A (en) * 1993-11-02 1996-08-20 National Semiconductor Corporation Method of automatic retransmission of frames in a local area network
US5732286A (en) * 1995-08-10 1998-03-24 Cirrus Logic, Inc. FIFO based receive packet throttle for receiving long strings of short data packets
GB2331895B (en) 1997-11-27 2000-03-29 Connell Anne O Testing data packets
GB2331896B (en) * 1997-11-27 2000-03-29 Connell Anne O Last-in first out data stacks and processing data using such data stacks
GB2331894B (en) 1997-11-27 2000-03-29 Connell Anne O Analysis of data streams
US6477143B1 (en) 1998-01-25 2002-11-05 Dror Ginossar Method and apparatus for packet network congestion avoidance and control
US6631484B1 (en) * 1998-03-31 2003-10-07 Lsi Logic Corporation System for packet communication where received packet is stored either in a FIFO or in buffer storage based on size of received packet
US7088680B1 (en) * 1999-01-11 2006-08-08 Advanced Micro Devices, Inc. System and method for digital communication via a time division multiplexed serial data stream
US6651107B1 (en) * 1999-09-21 2003-11-18 Intel Corporation Reduced hardware network adapter and communication
US7200696B2 (en) * 2001-04-06 2007-04-03 International Business Machines Corporation System method structure in network processor that indicates last data buffer of frame packet by last flag bit that is either in first or second position
US7162553B1 (en) * 2004-10-01 2007-01-09 Altera Corporation Correlating high-speed serial interface data and FIFO status signals in programmable logic devices
FR2906428A1 (fr) * 2006-09-26 2008-03-28 Canon Kk Procede, dispositif et application logicielle pour la transmission de paquets de donnees dands un systeme de communication.
JP5036353B2 (ja) * 2007-03-13 2012-09-26 オンセミコンダクター・トレーディング・リミテッド データ再生装置及びデータ再生方法
US8984157B2 (en) * 2012-07-18 2015-03-17 International Business Machines Corporation Network analysis in a file transfer system
US10439639B2 (en) 2016-12-28 2019-10-08 Intel Corporation Seemingly monolithic interface between separate integrated circuit die

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4016367A (en) * 1975-04-11 1977-04-05 Sperry Rand Corporation Communication multiplexer module
US4168469A (en) * 1977-10-04 1979-09-18 Ncr Corporation Digital data communication adapter
US4225919A (en) * 1978-06-30 1980-09-30 Motorola, Inc. Advanced data link controller
US4920534A (en) * 1986-02-28 1990-04-24 At&T Bell Laboratories System for controllably eliminating bits from packet information field based on indicator in header and amount of data in packet buffer
US4942515A (en) * 1986-03-31 1990-07-17 Wang Laboratories, Inc. Serial communications controller with FIFO register for storing supplemental data and counter for counting number of words within each transferred frame
DE3777797D1 (de) * 1987-01-28 1992-04-30 Ibm Vorrichtung zur vermittlung zwischen kanaelen fuer synchronen nachrichtenverkehr und zur vermittlung von asynchronen datenpaketen.
EP0285330A3 (de) * 1987-04-03 1989-09-06 Advanced Micro Devices, Inc. Daten-Protokoll-Steuerung

Also Published As

Publication number Publication date
EP0647082A2 (de) 1995-04-05
US4852088A (en) 1989-07-25
JP2719522B2 (ja) 1998-02-25
EP0647082A3 (de) 1995-05-31
DE3856486D1 (de) 2001-10-04
JPS63257857A (ja) 1988-10-25
EP0647082B1 (de) 2001-08-29
EP0290129A3 (de) 1990-01-24
DE3856486T2 (de) 2002-05-23
EP0290129A2 (de) 1988-11-09

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Legal Events

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RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties