ATE206219T1 - Verteilte verriegelungsoperation zum exklusiven speicherzugang während nicht elementaren operationen - Google Patents
Verteilte verriegelungsoperation zum exklusiven speicherzugang während nicht elementaren operationenInfo
- Publication number
- ATE206219T1 ATE206219T1 AT98957562T AT98957562T ATE206219T1 AT E206219 T1 ATE206219 T1 AT E206219T1 AT 98957562 T AT98957562 T AT 98957562T AT 98957562 T AT98957562 T AT 98957562T AT E206219 T1 ATE206219 T1 AT E206219T1
- Authority
- AT
- Austria
- Prior art keywords
- messages
- processor
- memory
- message
- memory access
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
- G06F9/524—Deadlock detection or avoidance
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0815—Cache consistency protocols
- G06F12/0817—Cache consistency protocols using directory methods
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Multi Processors (AREA)
- Computer And Data Communications (AREA)
- Lock And Its Accessories (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/964,623 US6092156A (en) | 1997-11-05 | 1997-11-05 | System and method for avoiding deadlocks utilizing split lock operations to provide exclusive access to memory during non-atomic operations |
| PCT/US1998/023468 WO1999023559A1 (en) | 1997-11-05 | 1998-11-04 | Split lock operation to provide exclusive access to memory during non-atomic operations |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ATE206219T1 true ATE206219T1 (de) | 2001-10-15 |
Family
ID=25508783
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AT98957562T ATE206219T1 (de) | 1997-11-05 | 1998-11-04 | Verteilte verriegelungsoperation zum exklusiven speicherzugang während nicht elementaren operationen |
Country Status (9)
| Country | Link |
|---|---|
| US (2) | US6092156A (de) |
| EP (1) | EP1029271B1 (de) |
| JP (1) | JP3703716B2 (de) |
| KR (1) | KR100381618B1 (de) |
| AT (1) | ATE206219T1 (de) |
| AU (1) | AU1379299A (de) |
| BR (1) | BR9814845A (de) |
| DE (1) | DE69801842T2 (de) |
| WO (1) | WO1999023559A1 (de) |
Families Citing this family (38)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6336159B1 (en) * | 1997-06-25 | 2002-01-01 | Intel Corporation | Method and apparatus for transferring data in source-synchronous protocol and transferring signals in common clock protocol in multiple agent processing system |
| US6092156A (en) * | 1997-11-05 | 2000-07-18 | Unisys Corporation | System and method for avoiding deadlocks utilizing split lock operations to provide exclusive access to memory during non-atomic operations |
| US6546439B1 (en) * | 1998-12-09 | 2003-04-08 | Advanced Micro Devices, Inc. | Method and system for improved data access |
| US6263409B1 (en) * | 1998-12-22 | 2001-07-17 | Unisys Corporation | Data processing system and method for substituting one type of request for another for increased performance when processing back-to-back requests of certain types |
| JP2001184295A (ja) * | 1999-12-27 | 2001-07-06 | Toshiba Corp | 周辺装置および計算機システム |
| US6609171B1 (en) | 1999-12-29 | 2003-08-19 | Intel Corporation | Quad pumped bus architecture and protocol |
| US6826619B1 (en) | 2000-08-21 | 2004-11-30 | Intel Corporation | Method and apparatus for preventing starvation in a multi-node architecture |
| US6487643B1 (en) | 2000-09-29 | 2002-11-26 | Intel Corporation | Method and apparatus for preventing starvation in a multi-node architecture |
| US6772298B2 (en) | 2000-12-20 | 2004-08-03 | Intel Corporation | Method and apparatus for invalidating a cache line without data return in a multi-node architecture |
| US6791412B2 (en) * | 2000-12-28 | 2004-09-14 | Intel Corporation | Differential amplifier output stage |
| US7234029B2 (en) * | 2000-12-28 | 2007-06-19 | Intel Corporation | Method and apparatus for reducing memory latency in a cache coherent multi-node architecture |
| US20020087775A1 (en) * | 2000-12-29 | 2002-07-04 | Looi Lily P. | Apparatus and method for interrupt delivery |
| US6721918B2 (en) | 2000-12-29 | 2004-04-13 | Intel Corporation | Method and apparatus for encoding a bus to minimize simultaneous switching outputs effect |
| US20020087766A1 (en) * | 2000-12-29 | 2002-07-04 | Akhilesh Kumar | Method and apparatus to implement a locked-bus transaction |
| US6742160B2 (en) | 2001-02-14 | 2004-05-25 | Intel Corporation | Checkerboard parity techniques for a multi-pumped bus |
| US6971098B2 (en) | 2001-06-27 | 2005-11-29 | Intel Corporation | Method and apparatus for managing transaction requests in a multi-node architecture |
| GB0118294D0 (en) * | 2001-07-27 | 2001-09-19 | Ibm | Method and system for deadlock detection and avoidance |
| US6892258B1 (en) * | 2001-10-26 | 2005-05-10 | Lsi Logic Corporation | Hardware semaphores for a multi-processor system within a shared memory architecture |
| US6986005B2 (en) * | 2001-12-31 | 2006-01-10 | Hewlett-Packard Development Company, L.P. | Low latency lock for multiprocessor computer system |
| US7085889B2 (en) * | 2002-03-22 | 2006-08-01 | Intel Corporation | Use of a context identifier in a cache memory |
| US7114042B2 (en) | 2003-05-22 | 2006-09-26 | International Business Machines Corporation | Method to provide atomic update primitives in an asymmetric heterogeneous multiprocessor environment |
| US6973548B1 (en) * | 2003-06-20 | 2005-12-06 | Unisys Corporation | Data acceleration mechanism for a multiprocessor shared memory system |
| WO2005066805A1 (ja) * | 2003-12-26 | 2005-07-21 | Fujitsu Limited | 共通メモリアクセス方法及びそれを用いたマルチプロセッサ・システム |
| US7953932B2 (en) * | 2008-02-13 | 2011-05-31 | International Business Machines Corporation | System and method for avoiding deadlocks when performing storage updates in a multi-processor environment |
| US8605099B2 (en) * | 2008-03-31 | 2013-12-10 | Intel Corporation | Partition-free multi-socket memory system architecture |
| US9026993B2 (en) * | 2008-06-27 | 2015-05-05 | Microsoft Technology Licensing, Llc | Immutable types in imperitive language |
| US9424013B2 (en) * | 2008-12-29 | 2016-08-23 | Oracle America, Inc. | System and method for reducing transactional abort rates using compiler optimization techniques |
| US8799572B2 (en) | 2009-04-20 | 2014-08-05 | Microsoft Corporation | Sliding-window multi-class striping |
| US9569282B2 (en) | 2009-04-24 | 2017-02-14 | Microsoft Technology Licensing, Llc | Concurrent mutation of isolated object graphs |
| US8103638B2 (en) * | 2009-05-07 | 2012-01-24 | Microsoft Corporation | Partitioning of contended synchronization objects |
| US8316369B2 (en) | 2009-12-29 | 2012-11-20 | Microsoft Corporation | Dataflow component scheduling using reader/writer semantics |
| US8566544B2 (en) * | 2009-12-29 | 2013-10-22 | Microsoft Corporation | Compiler-enforced agent access restriction |
| US8695003B2 (en) | 2009-12-29 | 2014-04-08 | Microsoft Corporation | Method for managing data accessibility by scheduling three types of executable agents associated with pre-defined access rights within a domain |
| CN103049422B (zh) * | 2012-12-17 | 2013-11-27 | 浪潮电子信息产业股份有限公司 | 一种具有多cache一致性域的多处理器节点系统构建方法 |
| US9098269B2 (en) * | 2013-01-04 | 2015-08-04 | Microsoft Technology Licensing, Llc | System and method to ensure resource access safety with immutable object types |
| US10102000B2 (en) * | 2016-04-01 | 2018-10-16 | Intel Corporation | Apparatus and method for non-serializing split locks |
| CN111258644B (zh) * | 2018-11-30 | 2022-08-09 | 上海寒武纪信息科技有限公司 | 数据处理方法、处理器、数据处理装置及存储介质 |
| CN112579323B (zh) * | 2020-12-25 | 2025-08-01 | 珠海全志科技股份有限公司 | 一种异构多核的异步通信方法及装置 |
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| US4000485A (en) * | 1975-06-30 | 1976-12-28 | Honeywell Information Systems, Inc. | Data processing system providing locked operation of shared resources |
| US4488217A (en) * | 1979-03-12 | 1984-12-11 | Digital Equipment Corporation | Data processing system with lock-unlock instruction facility |
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| US4466059A (en) * | 1981-10-15 | 1984-08-14 | International Business Machines Corporation | Method and apparatus for limiting data occupancy in a cache |
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| JP2783164B2 (ja) * | 1994-09-14 | 1998-08-06 | 日本電気株式会社 | 通信網 |
| US5717942A (en) * | 1994-12-27 | 1998-02-10 | Unisys Corporation | Reset for independent partitions within a computer system |
| US5838955A (en) * | 1995-05-03 | 1998-11-17 | Apple Computer, Inc. | Controller for providing access to a video frame buffer in split-bus transaction environment |
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| US6092156A (en) * | 1997-11-05 | 2000-07-18 | Unisys Corporation | System and method for avoiding deadlocks utilizing split lock operations to provide exclusive access to memory during non-atomic operations |
| KR100582782B1 (ko) * | 1998-08-28 | 2006-08-23 | 엘지엔시스(주) | 캐쉬 일관성 유지 방법 |
-
1997
- 1997-11-05 US US08/964,623 patent/US6092156A/en not_active Expired - Lifetime
-
1998
- 1998-11-04 AU AU13792/99A patent/AU1379299A/en not_active Abandoned
- 1998-11-04 KR KR10-2000-7004751A patent/KR100381618B1/ko not_active Expired - Fee Related
- 1998-11-04 WO PCT/US1998/023468 patent/WO1999023559A1/en not_active Ceased
- 1998-11-04 AT AT98957562T patent/ATE206219T1/de not_active IP Right Cessation
- 1998-11-04 DE DE69801842T patent/DE69801842T2/de not_active Expired - Fee Related
- 1998-11-04 BR BR9814845-1A patent/BR9814845A/pt active Search and Examination
- 1998-11-04 JP JP2000519354A patent/JP3703716B2/ja not_active Expired - Fee Related
- 1998-11-04 EP EP98957562A patent/EP1029271B1/de not_active Expired - Lifetime
-
2000
- 2000-06-20 US US09/597,621 patent/US6389515B1/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| US6092156A (en) | 2000-07-18 |
| DE69801842D1 (de) | 2001-10-31 |
| KR20010031689A (ko) | 2001-04-16 |
| DE69801842T2 (de) | 2002-04-11 |
| US6389515B1 (en) | 2002-05-14 |
| JP2001522087A (ja) | 2001-11-13 |
| AU1379299A (en) | 1999-05-24 |
| EP1029271A1 (de) | 2000-08-23 |
| KR100381618B1 (ko) | 2003-04-26 |
| JP3703716B2 (ja) | 2005-10-05 |
| WO1999023559A1 (en) | 1999-05-14 |
| BR9814845A (pt) | 2000-10-03 |
| EP1029271B1 (de) | 2001-09-26 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |