ATE210313T1 - Vereinheitlicher gleitkommadatenpfad und ganzzahldatenpfad für einen risc-prozessor - Google Patents

Vereinheitlicher gleitkommadatenpfad und ganzzahldatenpfad für einen risc-prozessor

Info

Publication number
ATE210313T1
ATE210313T1 AT94915938T AT94915938T ATE210313T1 AT E210313 T1 ATE210313 T1 AT E210313T1 AT 94915938 T AT94915938 T AT 94915938T AT 94915938 T AT94915938 T AT 94915938T AT E210313 T1 ATE210313 T1 AT E210313T1
Authority
AT
Austria
Prior art keywords
data path
unified
integer
risc processor
floating point
Prior art date
Application number
AT94915938T
Other languages
English (en)
Inventor
Andre Kowalczyk
Norman K P Yeung
Original Assignee
Mips Tech Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mips Tech Inc filed Critical Mips Tech Inc
Application granted granted Critical
Publication of ATE210313T1 publication Critical patent/ATE210313T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G06F9/30014—Arithmetic instructions with variable precision
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
AT94915938T 1993-05-17 1994-04-28 Vereinheitlicher gleitkommadatenpfad und ganzzahldatenpfad für einen risc-prozessor ATE210313T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/063,183 US5450607A (en) 1993-05-17 1993-05-17 Unified floating point and integer datapath for a RISC processor
PCT/US1994/004701 WO1994027205A1 (en) 1993-05-17 1994-04-28 Unified floating point and integer datapath for risc processor

Publications (1)

Publication Number Publication Date
ATE210313T1 true ATE210313T1 (de) 2001-12-15

Family

ID=22047502

Family Applications (1)

Application Number Title Priority Date Filing Date
AT94915938T ATE210313T1 (de) 1993-05-17 1994-04-28 Vereinheitlicher gleitkommadatenpfad und ganzzahldatenpfad für einen risc-prozessor

Country Status (6)

Country Link
US (1) US5450607A (de)
EP (1) EP0699318B1 (de)
JP (1) JPH09507592A (de)
AT (1) ATE210313T1 (de)
DE (1) DE69429342T2 (de)
WO (1) WO1994027205A1 (de)

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US5826074A (en) * 1996-11-22 1998-10-20 S3 Incorporated Extenstion of 32-bit architecture for 64-bit addressing with shared super-page register
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US6035388A (en) 1997-06-27 2000-03-07 Sandcraft, Inc. Method and apparatus for dual issue of program instructions to symmetric multifunctional execution units
US6216218B1 (en) 1997-11-03 2001-04-10 Donald L. Sollars Processor having a datapath and control logic constituted with basis execution blocks
US6292886B1 (en) * 1998-10-12 2001-09-18 Intel Corporation Scalar hardware for performing SIMD operations
US6321327B1 (en) 1998-12-30 2001-11-20 Intel Corporation Method for setting a bit associated with each component of packed floating-pint operand that is normalized in SIMD operations
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US10973397B2 (en) 1999-03-01 2021-04-13 West View Research, Llc Computerized information collection and processing apparatus
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US6732203B2 (en) * 2000-01-31 2004-05-04 Intel Corporation Selectively multiplexing memory coupling global bus data bits to narrower functional unit coupling local bus
US6904446B2 (en) * 2001-08-24 2005-06-07 Freescale Semiconductor, Inc. Floating point multiplier/accumulator with reduced latency and method thereof
US7003630B1 (en) 2002-06-27 2006-02-21 Mips Technologies, Inc. Mechanism for proxy management of multiprocessor storage hierarchies
US7017025B1 (en) * 2002-06-27 2006-03-21 Mips Technologies, Inc. Mechanism for proxy management of multiprocessor virtual memory
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US7415601B2 (en) * 2002-06-28 2008-08-19 Motorola, Inc. Method and apparatus for elimination of prolog and epilog instructions in a vector processor using data validity tags and sink counters
US7140019B2 (en) * 2002-06-28 2006-11-21 Motorola, Inc. Scheduler of program instructions for streaming vector processor having interconnected functional units
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US7373369B2 (en) * 2003-06-05 2008-05-13 International Business Machines Corporation Advanced execution of extended floating-point add operations in a narrow dataflow
US7290122B2 (en) * 2003-08-29 2007-10-30 Motorola, Inc. Dataflow graph compression for power reduction in a vector processor
US7610466B2 (en) * 2003-09-05 2009-10-27 Freescale Semiconductor, Inc. Data processing system using independent memory and register operand size specifiers and method thereof
US7315932B2 (en) * 2003-09-08 2008-01-01 Moyer William C Data processing system having instruction specifiers for SIMD register operands and method thereof
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US9304767B2 (en) * 2009-06-02 2016-04-05 Oracle America, Inc. Single cycle data movement between general purpose and floating-point registers
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CN107977227B (zh) * 2016-10-21 2024-07-02 超威半导体公司 包括不同指令类型的独立硬件数据路径的管线
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Also Published As

Publication number Publication date
EP0699318A4 (de) 1997-11-12
EP0699318A1 (de) 1996-03-06
EP0699318B1 (de) 2001-12-05
WO1994027205A1 (en) 1994-11-24
JPH09507592A (ja) 1997-07-29
DE69429342T2 (de) 2002-05-23
US5450607A (en) 1995-09-12
DE69429342D1 (de) 2002-01-17

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