ATE229667T1 - Synchron- mehrphasen- taktverteilungssystem - Google Patents

Synchron- mehrphasen- taktverteilungssystem

Info

Publication number
ATE229667T1
ATE229667T1 AT99943626T AT99943626T ATE229667T1 AT E229667 T1 ATE229667 T1 AT E229667T1 AT 99943626 T AT99943626 T AT 99943626T AT 99943626 T AT99943626 T AT 99943626T AT E229667 T1 ATE229667 T1 AT E229667T1
Authority
AT
Austria
Prior art keywords
distribution system
clock
clock distribution
phase clock
datapath
Prior art date
Application number
AT99943626T
Other languages
English (en)
Inventor
Ivan E Sutherland
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Application granted granted Critical
Publication of ATE229667T1 publication Critical patent/ATE229667T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/06—Clock generators producing several clock signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
  • Manipulation Of Pulses (AREA)
  • Logic Circuits (AREA)
AT99943626T 1998-09-04 1999-08-16 Synchron- mehrphasen- taktverteilungssystem ATE229667T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/146,810 US6188262B1 (en) 1998-09-04 1998-09-04 Synchronous polyphase clock distribution system
PCT/US1999/016997 WO2000014621A1 (en) 1998-09-04 1999-08-16 Synchronous polyphase clock distribution system

Publications (1)

Publication Number Publication Date
ATE229667T1 true ATE229667T1 (de) 2002-12-15

Family

ID=22519090

Family Applications (1)

Application Number Title Priority Date Filing Date
AT99943626T ATE229667T1 (de) 1998-09-04 1999-08-16 Synchron- mehrphasen- taktverteilungssystem

Country Status (7)

Country Link
US (1) US6188262B1 (de)
EP (1) EP1116087B1 (de)
JP (1) JP2002524790A (de)
AT (1) ATE229667T1 (de)
AU (1) AU5668599A (de)
DE (1) DE69904493T2 (de)
WO (1) WO2000014621A1 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6304125B1 (en) * 1998-09-04 2001-10-16 Sun Microsystems, Inc. Method for generating and distribution of polyphase clock signals
US6580303B1 (en) * 2000-08-02 2003-06-17 Sun Microsystems, Inc. Datapath control circuit with adjustable delay elements
US6668357B2 (en) * 2001-06-29 2003-12-23 Fujitsu Limited Cold clock power reduction
JP2004303195A (ja) * 2003-03-19 2004-10-28 Seiko Epson Corp シートコンピュータ、ウェアラブルコンピュータ、ディスプレイ装置及びこれらの製造方法並びに電子機器
US6954093B2 (en) * 2003-03-27 2005-10-11 Micronas Gmbh Clocking scheme and clock system for a monolithic integrated circuit
US20070013425A1 (en) * 2005-06-30 2007-01-18 Burr James B Lower minimum retention voltage storage elements
US8701023B1 (en) 2006-02-16 2014-04-15 Cypress Semiconductor Corporation Global parameter management graphical user interface (GUI) for embedded application design
US7592836B1 (en) * 2006-03-31 2009-09-22 Masleid Robert P Multi-write memory circuit with multiple data inputs
US8067970B2 (en) * 2006-03-31 2011-11-29 Masleid Robert P Multi-write memory circuit with a data input and a clock input
US8700818B2 (en) * 2006-09-29 2014-04-15 Mosaid Technologies Incorporated Packet based ID generation for serially interconnected devices
JP5181999B2 (ja) * 2008-10-10 2013-04-10 ソニー株式会社 固体撮像素子、光学装置、信号処理装置及び信号処理システム
JP5413216B2 (ja) * 2010-01-25 2014-02-12 富士通株式会社 遅延時間差測定回路
US10073938B2 (en) * 2016-06-29 2018-09-11 International Business Machines Corporation Integrated circuit design verification

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5787620A (en) * 1980-11-20 1982-06-01 Fujitsu Ltd Clock generating circuit
JPS59121697A (ja) * 1982-12-27 1984-07-13 Toshiba Corp シフトレジスタ
US4700347A (en) * 1985-02-13 1987-10-13 Bolt Beranek And Newman Inc. Digital phase adjustment
JP2570471B2 (ja) * 1990-06-25 1997-01-08 日本電気株式会社 クロックドライバー回路
US5306962A (en) * 1990-11-27 1994-04-26 Hewlett-Packard Company Qualified non-overlapping clock generator to provide control lines with non-overlapping clock timing
JPH07273618A (ja) * 1994-03-30 1995-10-20 Nec Corp クロックドライバ回路

Also Published As

Publication number Publication date
EP1116087B1 (de) 2002-12-11
DE69904493T2 (de) 2003-09-11
WO2000014621A9 (en) 2000-08-10
WO2000014621A1 (en) 2000-03-16
DE69904493D1 (de) 2003-01-23
EP1116087A1 (de) 2001-07-18
JP2002524790A (ja) 2002-08-06
AU5668599A (en) 2000-03-27
US6188262B1 (en) 2001-02-13

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Legal Events

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