ATE239255T1 - Prozessor oder zentraleinheit mit internem register für peripheriezustand - Google Patents

Prozessor oder zentraleinheit mit internem register für peripheriezustand

Info

Publication number
ATE239255T1
ATE239255T1 AT98965007T AT98965007T ATE239255T1 AT E239255 T1 ATE239255 T1 AT E239255T1 AT 98965007 T AT98965007 T AT 98965007T AT 98965007 T AT98965007 T AT 98965007T AT E239255 T1 ATE239255 T1 AT E239255T1
Authority
AT
Austria
Prior art keywords
processor
status
central unit
internal register
status register
Prior art date
Application number
AT98965007T
Other languages
English (en)
Inventor
Dean A Klein
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/131,497 external-priority patent/US6189049B1/en
Priority claimed from US09/131,922 external-priority patent/US6374320B1/en
Priority claimed from US09/131,446 external-priority patent/US6233627B1/en
Priority claimed from US09/131,447 external-priority patent/US6219720B1/en
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Application granted granted Critical
Publication of ATE239255T1 publication Critical patent/ATE239255T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G06F13/126—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine and has means for transferring I/O instructions and statuses between control unit and main processor

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Bus Control (AREA)
  • Multi Processors (AREA)
AT98965007T 1998-08-10 1998-12-29 Prozessor oder zentraleinheit mit internem register für peripheriezustand ATE239255T1 (de)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US09/131,497 US6189049B1 (en) 1998-08-10 1998-08-10 Method for operating processor with internal register for peripheral status
US09/131,922 US6374320B1 (en) 1998-08-10 1998-08-10 Method for operating core logic unit with internal register for peripheral status
US09/131,446 US6233627B1 (en) 1998-08-10 1998-08-10 Processor with internal register for peripheral status
US09/131,447 US6219720B1 (en) 1998-08-10 1998-08-10 Core logic unit with internal register for peripheral status
PCT/US1998/027784 WO2000010094A1 (en) 1998-08-10 1998-12-29 Processor or core logic unit with internal register for peripheral status

Publications (1)

Publication Number Publication Date
ATE239255T1 true ATE239255T1 (de) 2003-05-15

Family

ID=27494909

Family Applications (1)

Application Number Title Priority Date Filing Date
AT98965007T ATE239255T1 (de) 1998-08-10 1998-12-29 Prozessor oder zentraleinheit mit internem register für peripheriezustand

Country Status (8)

Country Link
EP (1) EP1119814B1 (de)
JP (1) JP4490585B2 (de)
KR (1) KR100453262B1 (de)
AT (1) ATE239255T1 (de)
AU (1) AU2020799A (de)
DE (1) DE69814182T2 (de)
TW (1) TW413776B (de)
WO (1) WO2000010094A1 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10115885B4 (de) * 2001-03-30 2006-09-21 Infineon Technologies Ag Anordnung zur Priorisierung eines Interrupts
EP1359509A1 (de) * 2002-04-29 2003-11-05 Siemens Aktiengesellschaft Mehrprozessorsystem
US7610061B2 (en) * 2003-09-20 2009-10-27 Samsung Electronics Co., Ltd. Communication device and method having a common platform
US20060230226A1 (en) * 2005-04-12 2006-10-12 M-Systems Flash Disk Pioneers, Ltd. Hard disk drive with optional cache memory
JP5790043B2 (ja) * 2011-03-14 2015-10-07 株式会社リコー データ転送システム及びデータ転送方法
US9134767B2 (en) * 2013-08-07 2015-09-15 Chin-Hsing Horng Structure of planetary type dual-shaft hinge
US11249904B2 (en) * 2017-11-17 2022-02-15 Mitsubishi Heavy Industries Machinery Systems, Ltd. Information processing system and information processing method to be executed by information processing system
KR102487899B1 (ko) 2021-02-03 2023-01-12 효성티앤에스 주식회사 금융자동화기기의 호스트와 디바이스 간 통신 방법

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6158037A (ja) * 1984-07-23 1986-03-25 Fujitsu Ltd サ−ビスプロセツサへの割り込み制御方式
US4768149A (en) * 1985-08-29 1988-08-30 International Business Machines Corporation System for managing a plurality of shared interrupt handlers in a linked-list data structure
JPH02230356A (ja) * 1989-03-02 1990-09-12 Nec Corp 情報処理装置のバス拡張装置
US5317707A (en) * 1989-10-20 1994-05-31 Texas Instruments Incorporated Expanded memory interface for supporting expanded, conventional or extended memory for communication between an application processor and an external processor
EP0530310A4 (en) * 1990-05-18 1993-07-21 Star Semiconductor Corporation Programmable signal processor architecture
US5463752A (en) * 1992-09-23 1995-10-31 International Business Machines Corporation Method and system for enhancing the efficiency of communication between multiple direct access storage devices and a storage system controller
US5678025A (en) * 1992-12-30 1997-10-14 Intel Corporation Cache coherency maintenance of non-cache supporting buses
EP0640929A3 (de) * 1993-08-30 1995-11-29 Advanced Micro Devices Inc Zwischenprozessorkommunikation durch RAM-Postamt.
US5548730A (en) * 1994-09-20 1996-08-20 Intel Corporation Intelligent bus bridge for input/output subsystems in a computer system
JPH0991152A (ja) * 1995-09-20 1997-04-04 Toshiba Corp コンピュータシステムおよびそのシステムで使用されるマルチファンクションデバイス
JPH1021182A (ja) * 1996-06-28 1998-01-23 Nec Eng Ltd 割り込み処理方式および制御装置
US5852743A (en) * 1996-07-12 1998-12-22 Twinhead International Corp. Method and apparatus for connecting a plug-and-play peripheral device to a computer

Also Published As

Publication number Publication date
TW413776B (en) 2000-12-01
DE69814182T2 (de) 2004-04-01
JP2002522846A (ja) 2002-07-23
DE69814182D1 (de) 2003-06-05
KR100453262B1 (ko) 2004-10-15
AU2020799A (en) 2000-03-06
EP1119814B1 (de) 2003-05-02
KR20010088787A (ko) 2001-09-28
EP1119814A1 (de) 2001-08-01
EP1119814A4 (de) 2001-09-26
JP4490585B2 (ja) 2010-06-30
WO2000010094A1 (en) 2000-02-24

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Legal Events

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