ATE241230T1 - Kompensationsschaltung für geringe phasenverschiebungen in phasensregelschleifen - Google Patents

Kompensationsschaltung für geringe phasenverschiebungen in phasensregelschleifen

Info

Publication number
ATE241230T1
ATE241230T1 AT00950568T AT00950568T ATE241230T1 AT E241230 T1 ATE241230 T1 AT E241230T1 AT 00950568 T AT00950568 T AT 00950568T AT 00950568 T AT00950568 T AT 00950568T AT E241230 T1 ATE241230 T1 AT E241230T1
Authority
AT
Austria
Prior art keywords
input signal
output signals
output
phase
compensation circuit
Prior art date
Application number
AT00950568T
Other languages
English (en)
Inventor
Chung-Hsiao R Wu
Drew G Doblar
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Application granted granted Critical
Publication of ATE241230T1 publication Critical patent/ATE241230T1/de

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Networks Using Active Elements (AREA)
AT00950568T 1999-07-22 2000-07-21 Kompensationsschaltung für geringe phasenverschiebungen in phasensregelschleifen ATE241230T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/359,952 US6462593B2 (en) 1999-07-22 1999-07-22 Compensation circuit for low phase offset for phase-locked loops
PCT/US2000/019995 WO2001008312A1 (en) 1999-07-22 2000-07-21 Compensation circuit for low phase offset for phase-locked loops

Publications (1)

Publication Number Publication Date
ATE241230T1 true ATE241230T1 (de) 2003-06-15

Family

ID=23415953

Family Applications (1)

Application Number Title Priority Date Filing Date
AT00950568T ATE241230T1 (de) 1999-07-22 2000-07-21 Kompensationsschaltung für geringe phasenverschiebungen in phasensregelschleifen

Country Status (7)

Country Link
US (1) US6462593B2 (de)
EP (1) EP1196997B1 (de)
JP (1) JP2003505970A (de)
AT (1) ATE241230T1 (de)
AU (1) AU6365800A (de)
DE (1) DE60002877T2 (de)
WO (1) WO2001008312A1 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7082178B2 (en) * 2001-12-14 2006-07-25 Seiko Epson Corporation Lock detector circuit for dejitter phase lock loop (PLL)
DE10255863B4 (de) * 2002-11-29 2008-07-31 Infineon Technologies Ag Phasenregelschleife
US7042252B2 (en) * 2004-04-23 2006-05-09 Brian Jeffrey Galloway Correcting for DC offset in a phase locked loop
CN114679173B (zh) * 2021-10-06 2022-08-30 绍兴圆方半导体有限公司 锁相环和时钟同步系统

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3725793A (en) 1971-12-15 1973-04-03 Bell Telephone Labor Inc Clock synchronization arrangement employing delay devices
DE3218363A1 (de) 1982-05-15 1983-11-17 Howaldtswerke-Deutsche Werft Ag Hamburg Und Kiel, 2300 Kiel Schaltungsanordnung zur steuerung eines spannungsabhaengigen oszillators
US4599570A (en) 1982-07-21 1986-07-08 Sperry Corporation Phase detector with independent offset correction
JPH07114348B2 (ja) 1987-12-11 1995-12-06 日本電気株式会社 論理回路
JPH07120225B2 (ja) 1988-04-15 1995-12-20 富士通株式会社 半導体回路装置
US4989175A (en) 1988-11-25 1991-01-29 Unisys Corp. High speed on-chip clock phase generating system
US5058132A (en) 1989-10-26 1991-10-15 National Semiconductor Corporation Clock distribution system and technique
JP3208736B2 (ja) * 1991-11-08 2001-09-17 ソニー株式会社 Ｐｌｌ回路
US5307381A (en) 1991-12-27 1994-04-26 Intel Corporation Skew-free clock signal distribution network in a microprocessor
US5256994A (en) 1992-09-21 1993-10-26 Intel Corporation Programmable secondary clock generator
US5663685A (en) * 1996-03-29 1997-09-02 Bull Hn Information Systems Inc. Dual flip-flop detector type phase locked loop incorporating dynamic phase offset correction
DK124696A (da) * 1996-11-06 1998-05-07 Dsc Communications As Fremgangsmåde og apparat til sammenligning af to logiske signaler samt fremgangsmåde og apparat til frembringelse af et fas
US6154089A (en) * 1997-12-05 2000-11-28 Texas Instruments Incorporated Fast bus driver with reduced standby power consumption

Also Published As

Publication number Publication date
WO2001008312A1 (en) 2001-02-01
US20010013800A1 (en) 2001-08-16
EP1196997A1 (de) 2002-04-17
AU6365800A (en) 2001-02-13
JP2003505970A (ja) 2003-02-12
DE60002877T2 (de) 2004-03-11
EP1196997B1 (de) 2003-05-21
DE60002877D1 (de) 2003-06-26
US6462593B2 (en) 2002-10-08

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Legal Events

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