ATE262700T1 - Zwei-tor cam speicher für simultanen flash speicher betrieb - Google Patents

Zwei-tor cam speicher für simultanen flash speicher betrieb

Info

Publication number
ATE262700T1
ATE262700T1 AT01939217T AT01939217T ATE262700T1 AT E262700 T1 ATE262700 T1 AT E262700T1 AT 01939217 T AT01939217 T AT 01939217T AT 01939217 T AT01939217 T AT 01939217T AT E262700 T1 ATE262700 T1 AT E262700T1
Authority
AT
Austria
Prior art keywords
cam
cell
memory
memory cell
data bus
Prior art date
Application number
AT01939217T
Other languages
English (en)
Inventor
Ali Al-Shamma
Lee Cleveland
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of ATE262700T1 publication Critical patent/ATE262700T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
    • G11C29/789—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using non-volatile cells or latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
    • G11C15/04—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
    • G11C15/046—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements using non-volatile storage elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
AT01939217T 2000-05-31 2001-05-21 Zwei-tor cam speicher für simultanen flash speicher betrieb ATE262700T1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US20844900P 2000-05-31 2000-05-31
US09/829,657 US6396749B2 (en) 2000-05-31 2001-04-10 Dual-ported CAMs for a simultaneous operation flash memory
PCT/US2001/016393 WO2001093034A2 (en) 2000-05-31 2001-05-21 Dual-ported cams for a simultaneous operation flash memory

Publications (1)

Publication Number Publication Date
ATE262700T1 true ATE262700T1 (de) 2004-04-15

Family

ID=26903205

Family Applications (1)

Application Number Title Priority Date Filing Date
AT01939217T ATE262700T1 (de) 2000-05-31 2001-05-21 Zwei-tor cam speicher für simultanen flash speicher betrieb

Country Status (11)

Country Link
US (1) US6396749B2 (de)
EP (1) EP1290559B1 (de)
JP (1) JP4606694B2 (de)
KR (1) KR100915450B1 (de)
CN (1) CN1204497C (de)
AT (1) ATE262700T1 (de)
AU (1) AU2001264757A1 (de)
BR (1) BR0111245A (de)
DE (1) DE60102466T2 (de)
TW (1) TW587255B (de)
WO (1) WO2001093034A2 (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6492881B2 (en) * 2001-01-31 2002-12-10 Compaq Information Technologies Group, L.P. Single to differential logic level interface for computer systems
US6711720B2 (en) * 2002-03-14 2004-03-23 Hewlett-Packard Development Company, L.P. Method of optimizing high performance CMOS integrated circuit designs for power consumption and speed through genetic optimization
US6745371B2 (en) * 2002-03-15 2004-06-01 Sun Microsystems, Inc. Low Vt transistor substitution in a semiconductor device
US6845025B1 (en) 2003-03-21 2005-01-18 Netlogic Microsystems, Inc. Word line driver circuit for a content addressable memory
US7032200B1 (en) 2003-09-09 2006-04-18 Sun Microsystems, Inc. Low threshold voltage transistor displacement in a semiconductor device
US6973003B1 (en) 2003-10-01 2005-12-06 Advanced Micro Devices, Inc. Memory device and method
US7200693B2 (en) 2004-08-27 2007-04-03 Micron Technology, Inc. Memory system and method having unidirectional data buses
US7209405B2 (en) * 2005-02-23 2007-04-24 Micron Technology, Inc. Memory device and method having multiple internal data buses and memory bank interleaving
US20070028027A1 (en) * 2005-07-26 2007-02-01 Micron Technology, Inc. Memory device and method having separate write data and read data buses
US7301832B2 (en) * 2005-11-03 2007-11-27 Atmel Corporation Compact column redundancy CAM architecture for concurrent read and write operations in multi-segment memory arrays
US7567448B2 (en) * 2007-01-05 2009-07-28 Atmel Corporation Content addressable memory cell having a single floating gate transistor
JP2008234806A (ja) * 2007-03-23 2008-10-02 Toshiba Corp 半導体記憶装置およびそのリダンダンシ方法
WO2009079478A1 (en) * 2007-12-14 2009-06-25 Virident Systems, Inc. Distributing metadata across multiple different disruption regions within an asymmetric memory system
US7996736B2 (en) * 2008-10-26 2011-08-09 Sandisk 3D Llc Bad page marking strategy for fast readout in memory
US7911818B2 (en) * 2009-03-16 2011-03-22 Netlogic Microsystems, Inc. Content addressable memory having bidirectional lines that support passing read/write data and search data
US20140115422A1 (en) 2012-10-24 2014-04-24 Laurence H. Cooke Non-volatile memory error correction
US11972126B2 (en) * 2021-03-26 2024-04-30 Intel Corporation Data relocation for inline metadata
CN116110464B (zh) * 2021-11-11 2026-03-20 瑞昱半导体股份有限公司 存储器时分控制装置
US12531095B2 (en) * 2024-06-27 2026-01-20 Qualcomm Incorporated Memory with redundant read optimization

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02282999A (ja) * 1989-04-25 1990-11-20 Oki Micro Design Miyazaki:Kk 半導体メモリ装置
US5245572A (en) * 1991-07-30 1993-09-14 Intel Corporation Floating gate nonvolatile memory with reading while writing capability
FR2716743B1 (fr) * 1994-02-28 1996-09-27 Sgs Thomson Microelectronics Circuit de redondance de mémoire.
JP3059076B2 (ja) * 1995-06-19 2000-07-04 シャープ株式会社 不揮発性半導体記憶装置
US6317349B1 (en) * 1999-04-16 2001-11-13 Sandisk Corporation Non-volatile content addressable memory
US6484271B1 (en) * 1999-09-16 2002-11-19 Koninklijke Philips Electronics N.V. Memory redundancy techniques
US6307787B1 (en) * 2000-07-25 2001-10-23 Advanced Micro Devices, Inc. Burst read incorporating output based redundancy

Also Published As

Publication number Publication date
KR100915450B1 (ko) 2009-09-04
WO2001093034A2 (en) 2001-12-06
DE60102466T2 (de) 2005-02-24
EP1290559A2 (de) 2003-03-12
KR20030007812A (ko) 2003-01-23
WO2001093034A3 (en) 2002-05-02
EP1290559B1 (de) 2004-03-24
CN1204497C (zh) 2005-06-01
US6396749B2 (en) 2002-05-28
JP2003535430A (ja) 2003-11-25
JP4606694B2 (ja) 2011-01-05
CN1432153A (zh) 2003-07-23
DE60102466D1 (de) 2004-04-29
BR0111245A (pt) 2003-06-03
TW587255B (en) 2004-05-11
US20010048613A1 (en) 2001-12-06
AU2001264757A1 (en) 2001-12-11

Similar Documents

Publication Publication Date Title
ATE262700T1 (de) Zwei-tor cam speicher für simultanen flash speicher betrieb
JP4062247B2 (ja) 半導体記憶装置
DE60130437D1 (de) Simultaner mehrbank für flash-speicher
JP3999516B2 (ja) スタック・メモリ・パッケージを備えたメモリ拡張モジュール
JP4431977B2 (ja) メモリモジュールの自己テストおよび修復するためのシステムおよび方法
KR100851545B1 (ko) 커맨드 및 어드레스 핀을 갖는 낸드 플래시 메모리 및그것을 포함한 플래시 메모리 시스템
US5864505A (en) Random access memory with plural simultaneously operable banks
EP0264893A3 (de) Halbleiterspeicher
KR20030034496A (ko) 제1 또는 제2메모리 아키텍쳐로의 구현이 가능한 반도체메모리 장치 및 이를 이용한 메모리 시스템
JP2001325800A5 (de)
JPH04212796A (ja) 欠陥を許容できるシリアルメモリ
KR940022583A (ko) 병렬비트테스트모드내장 반도체 메모리
KR870000598A (ko) 메모리 테스트 회로
DE60308202D1 (de) Hochkompakter nichtflüchtiger speicher mit platz sparenden datenregistern und dessen betriebsverfahren
DE60004871D1 (de) Redundante doppelbank-architektur für einen simultanen flash-speicher
DE69329282D1 (de) Festkoerperspeichervorrichtung
US20040190347A1 (en) Dynamic column block selection
JP2024107179A5 (de)
DE60126800D1 (de) Burstread mit ausgangbasierter redundanz
US6629190B2 (en) Non-redundant nonvolatile memory and method for sequentially accessing the nonvolatile memory using shift registers to selectively bypass individual word lines
JPH1117098A (ja) メモリモジュール
CN103177751B (zh) 一种存储器阵列结构
US6707754B2 (en) Method of constructing a very wide, very fast distributed memory
KR100596821B1 (ko) 멀티 프로세서 기능을 지원하는 메모리 장치
JP3499120B2 (ja) 半導体記憶装置

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties