ATE275277T1 - Multiprozessorcomputer busschnittstellenadapter und methode - Google Patents

Multiprozessorcomputer busschnittstellenadapter und methode

Info

Publication number
ATE275277T1
ATE275277T1 AT01942224T AT01942224T ATE275277T1 AT E275277 T1 ATE275277 T1 AT E275277T1 AT 01942224 T AT01942224 T AT 01942224T AT 01942224 T AT01942224 T AT 01942224T AT E275277 T1 ATE275277 T1 AT E275277T1
Authority
AT
Austria
Prior art keywords
predictive
delay
interface adapter
delay element
base generator
Prior art date
Application number
AT01942224T
Other languages
English (en)
Inventor
Jennifer Y Chiao
Gary A Alvstad
Myles H Wakayama
Original Assignee
Broadcom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Broadcom Corp filed Critical Broadcom Corp
Application granted granted Critical
Publication of ATE275277T1 publication Critical patent/ATE275277T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0024—Peripheral component interconnect [PCI]

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Logic Circuits (AREA)
  • Bus Control (AREA)
  • Dc Digital Transmission (AREA)
  • Hardware Redundancy (AREA)
  • Multi Processors (AREA)
AT01942224T 2000-05-31 2001-05-25 Multiprozessorcomputer busschnittstellenadapter und methode ATE275277T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US20845300P 2000-05-31 2000-05-31
PCT/US2001/040810 WO2001093052A2 (en) 2000-05-31 2001-05-25 Multiprotocol computer bus interface adapter and method

Publications (1)

Publication Number Publication Date
ATE275277T1 true ATE275277T1 (de) 2004-09-15

Family

ID=22774664

Family Applications (1)

Application Number Title Priority Date Filing Date
AT01942224T ATE275277T1 (de) 2000-05-31 2001-05-25 Multiprozessorcomputer busschnittstellenadapter und methode

Country Status (6)

Country Link
US (2) US6829715B2 (de)
EP (1) EP1292894B1 (de)
AT (1) ATE275277T1 (de)
AU (1) AU2001275503A1 (de)
DE (1) DE60105297T2 (de)
WO (1) WO2001093052A2 (de)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6950897B2 (en) * 2001-02-23 2005-09-27 Hewlett-Packard Development Company, L.P. Method and apparatus for a dual mode PCI/PCI-X device
WO2002086747A1 (en) * 2001-04-24 2002-10-31 Broadcom Corporation Integrated gigabit ethernet pci-x controller
US7577857B1 (en) * 2001-08-29 2009-08-18 3Com Corporation High speed network interface with automatic power management with auto-negotiation
US20030061341A1 (en) * 2001-09-26 2003-03-27 Infineon Technologies North America Corp. Media cross conversion interface
US8190766B2 (en) 2002-05-09 2012-05-29 Broadcom Corporation Across-device communication protocol
KR100651566B1 (ko) * 2003-08-26 2006-11-28 삼성전자주식회사 이동통신 단말기에서 출력 버퍼링을 이용한 멀티미디어재생 장치 및 그 제어 방법
US7139965B2 (en) * 2003-10-08 2006-11-21 Hewlett-Packard Development Company, L.P. Bus device that concurrently synchronizes source synchronous data while performing error detection and correction
US7386648B2 (en) * 2003-10-24 2008-06-10 02 Micro International Limited PC card controller with reduced number of terminals
KR100514414B1 (ko) * 2003-11-20 2005-09-09 주식회사 하이닉스반도체 지연 동기 루프
TWI226552B (en) * 2003-11-20 2005-01-11 Rdc Semiconductor Co Ltd Bus integrating system
US7251740B2 (en) * 2004-01-23 2007-07-31 Intel Corporation Apparatus coupling two circuits having different supply voltage sources
CN100554987C (zh) * 2004-05-11 2009-10-28 株式会社爱德万测试 定时发生器以及半导体试验装置
US7180353B2 (en) * 2005-02-03 2007-02-20 Mediatek Incorporation Apparatus and method for low power clock distribution
US7716511B2 (en) * 2006-03-08 2010-05-11 Freescale Semiconductor, Inc. Dynamic timing adjustment in a circuit device
DE102007010771A1 (de) * 2007-03-06 2008-10-30 Robert Bosch Gmbh Verfahren zur Bestimmung einer asymmetrischen Signalverzögerung eines Signalpfades innerhalb einer integrierten Schaltung
US7940100B2 (en) * 2007-09-24 2011-05-10 Qualcomm, Incorporated Delay circuits matching delays of synchronous circuits
JP2011060385A (ja) * 2009-09-11 2011-03-24 Elpida Memory Inc 半導体装置及びその制御方法並びにデータ処理システム
US8713277B2 (en) 2010-06-01 2014-04-29 Apple Inc. Critical word forwarding with adaptive prediction
KR102087437B1 (ko) * 2013-06-17 2020-03-10 에스케이하이닉스 주식회사 수신장치를 포함하는 반도체시스템
DE102017208835A1 (de) * 2017-05-24 2018-11-29 Wago Verwaltungsgesellschaft Mbh Verarbeitung von Prozessdaten
US10867094B2 (en) * 2018-03-16 2020-12-15 Ambient Scientific Inc. Adjustable integrated circuits and methods for designing the same
US10712770B1 (en) * 2018-07-23 2020-07-14 Xilinx, Inc. Clock phase aligner for high speed data serializers
US11003203B2 (en) * 2018-07-23 2021-05-11 Xilinx, Inc. Circuits for and methods of calibrating a circuit in an integrated circuit device
DE102019208813A1 (de) * 2019-06-18 2020-12-24 Robert Bosch Gmbh Sicherheitsmodul für einen sicheren Betrieb einer Automatisierungssystembaugruppe

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Publication number Priority date Publication date Assignee Title
US4876702A (en) * 1988-07-28 1989-10-24 Hewlett-Packard Company Programmable time advance
US5652530A (en) * 1995-09-29 1997-07-29 Intel Corporation Method and apparatus for reducing clock-data skew by clock shifting
US6081146A (en) * 1996-09-25 2000-06-27 Kabushiki Kaisha Toshiba Interface circuit and interface circuit delay time controlling method
US6047383A (en) * 1998-01-23 2000-04-04 Intel Corporation Multiple internal phase-locked loops for synchronization of chipset components and subsystems operating at different frequencies
JP3502576B2 (ja) * 1998-07-24 2004-03-02 松下電器産業株式会社 クロック発生回路
US6636980B1 (en) * 1999-08-19 2003-10-21 International Business Machines Corporation System for launching data on a bus by using first clock for alternately selecting data from two data streams and using second clock for launching data thereafter
JP4397076B2 (ja) * 1999-08-20 2010-01-13 株式会社ルネサステクノロジ 半導体装置
US6553505B1 (en) * 2000-02-29 2003-04-22 Maxtor Corporation Method and apparatus for performing clock timing de-skew

Also Published As

Publication number Publication date
US6829715B2 (en) 2004-12-07
WO2001093052A2 (en) 2001-12-06
DE60105297D1 (de) 2004-10-07
US7366940B2 (en) 2008-04-29
DE60105297T2 (de) 2005-11-17
EP1292894A2 (de) 2003-03-19
US20050066212A1 (en) 2005-03-24
WO2001093052A3 (en) 2002-06-20
AU2001275503A1 (en) 2001-12-11
US20040221144A1 (en) 2004-11-04
EP1292894B1 (de) 2004-09-01

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