ATE280413T1 - Systeme, welche eine mischung aus paketartigem, kohärentem und nicht-kohärentem verkehr verwenden,um die übertragung zwischen systemen zu optimieren - Google Patents

Systeme, welche eine mischung aus paketartigem, kohärentem und nicht-kohärentem verkehr verwenden,um die übertragung zwischen systemen zu optimieren

Info

Publication number
ATE280413T1
ATE280413T1 AT02025686T AT02025686T ATE280413T1 AT E280413 T1 ATE280413 T1 AT E280413T1 AT 02025686 T AT02025686 T AT 02025686T AT 02025686 T AT02025686 T AT 02025686T AT E280413 T1 ATE280413 T1 AT E280413T1
Authority
AT
Austria
Prior art keywords
systems
coherent
interface
packetty
mixture
Prior art date
Application number
AT02025686T
Other languages
English (en)
Inventor
Barton J Sano
Joseph B Rowlands
Laurent R Moll
Manu Gulati
Original Assignee
Broadcom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Broadcom Corp filed Critical Broadcom Corp
Application granted granted Critical
Publication of ATE280413T1 publication Critical patent/ATE280413T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Multi Processors (AREA)
  • Two-Way Televisions, Distribution Of Moving Picture Or The Like (AREA)
  • Transmitters (AREA)
  • Mobile Radio Communication Systems (AREA)
AT02025686T 2001-11-20 2002-11-20 Systeme, welche eine mischung aus paketartigem, kohärentem und nicht-kohärentem verkehr verwenden,um die übertragung zwischen systemen zu optimieren ATE280413T1 (de)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US33178901P 2001-11-20 2001-11-20
US34471301P 2001-12-24 2001-12-24
US34877702P 2002-01-14 2002-01-14
US34871702P 2002-01-14 2002-01-14
US38074002P 2002-05-15 2002-05-15
US10/269,922 US7206879B2 (en) 2001-11-20 2002-10-11 Systems using mix of packet, coherent, and noncoherent traffic to optimize transmission between systems

Publications (1)

Publication Number Publication Date
ATE280413T1 true ATE280413T1 (de) 2004-11-15

Family

ID=27559477

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02025686T ATE280413T1 (de) 2001-11-20 2002-11-20 Systeme, welche eine mischung aus paketartigem, kohärentem und nicht-kohärentem verkehr verwenden,um die übertragung zwischen systemen zu optimieren

Country Status (4)

Country Link
US (2) US7206879B2 (de)
EP (1) EP1313024B1 (de)
AT (1) ATE280413T1 (de)
DE (1) DE60201650T2 (de)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7234029B2 (en) * 2000-12-28 2007-06-19 Intel Corporation Method and apparatus for reducing memory latency in a cache coherent multi-node architecture
US7752281B2 (en) * 2001-11-20 2010-07-06 Broadcom Corporation Bridges performing remote reads and writes as uncacheable coherent operations
US20040151170A1 (en) * 2003-01-31 2004-08-05 Manu Gulati Management of received data within host device using linked lists
US6981074B2 (en) * 2003-10-14 2005-12-27 Broadcom Corporation Descriptor-based load balancing
US20060129709A1 (en) * 2004-12-09 2006-06-15 International Business Machines Corporation Multipurpose scalable server communication link
US7499452B2 (en) * 2004-12-28 2009-03-03 International Business Machines Corporation Self-healing link sequence counts within a circular buffer
US7865624B1 (en) 2005-04-04 2011-01-04 Oracle America, Inc. Lookup mechanism based on link layer semantics
US7843926B1 (en) * 2005-04-05 2010-11-30 Oracle America, Inc. System for providing virtualization of network interfaces at various layers
US20070076685A1 (en) * 2005-09-30 2007-04-05 Pak-Lung Seto Programmable routing for frame-packet based frame processing
US7912998B2 (en) * 2006-01-06 2011-03-22 Hewlett-Packard Development Company, L.P. DMA access systems and methods
US7702743B1 (en) 2006-01-26 2010-04-20 Symantec Operating Corporation Supporting a weak ordering memory model for a virtual physical address space that spans multiple nodes
US7756943B1 (en) * 2006-01-26 2010-07-13 Symantec Operating Corporation Efficient data transfer between computers in a virtual NUMA system using RDMA
US11244727B2 (en) 2006-11-29 2022-02-08 Rambus Inc. Dynamic memory rank configuration
US7924938B2 (en) * 2007-09-24 2011-04-12 Wally Haas Context-sensitive overhead processor
US7930459B2 (en) * 2007-09-28 2011-04-19 Intel Corporation Coherent input output device
US8131944B2 (en) * 2008-05-30 2012-03-06 Intel Corporation Using criticality information to route cache coherency communications
US7970976B2 (en) * 2009-03-01 2011-06-28 Qualcomm Incorporated Remote memory access using reversible host/client interface
US8478877B2 (en) * 2010-02-24 2013-07-02 Oracle International Corporation Architecture-aware allocation of network buffers
US8135881B1 (en) * 2010-09-27 2012-03-13 Skyworks Solutions, Inc. Dynamically configurable serial data communication interface
US12411767B2 (en) * 2021-05-07 2025-09-09 Samsung Electronics Co., Ltd. Coherent memory system

Family Cites Families (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1982003931A1 (en) * 1981-04-27 1982-11-11 Kris Bryan Multi-master processor bus
US4788679A (en) 1986-09-02 1988-11-29 Nippon Telegraph And Telephone Corporation Packet switch with variable data transfer rate links
US5765011A (en) 1990-11-13 1998-06-09 International Business Machines Corporation Parallel processing system having a synchronous SIMD processing with processing elements emulating SIMD operation using individual instruction streams
US5963745A (en) 1990-11-13 1999-10-05 International Business Machines Corporation APAP I/O programmable router
US5797026A (en) * 1994-02-28 1998-08-18 Intel Corporation Method and apparatus for self-snooping a bus during a boundary transaction
US5634004A (en) 1994-05-16 1997-05-27 Network Programs, Inc. Directly programmable distribution element
DE59507871D1 (de) 1994-07-12 2000-04-06 Ascom Ag Vorrichtung zur Vermittlung in digitalen Datennetzen für asynchronen Transfermodus
EP0735487B1 (de) * 1995-03-31 2001-10-31 Sun Microsystems, Inc. Schnelle Zweitor-Cachesteuerungsschaltung für Datenprozessoren in einem paketvermittelten cachekohärenten Multiprozessorsystem
US5805920A (en) 1995-11-13 1998-09-08 Tandem Computers Incorporated Direct bulk data transfers
US5710907A (en) 1995-12-22 1998-01-20 Sun Microsystems, Inc. Hybrid NUMA COMA caching system and methods for selecting between the caching modes
US5887138A (en) 1996-07-01 1999-03-23 Sun Microsystems, Inc. Multiprocessing computer system employing local and global address spaces and COMA and NUMA access modes
US5878268A (en) 1996-07-01 1999-03-02 Sun Microsystems, Inc. Multiprocessing system configured to store coherency state within multiple subnodes of a processing node
US5813029A (en) 1996-07-09 1998-09-22 Micron Electronics, Inc. Upgradeable cache circuit using high speed multiplexer
US5961623A (en) * 1996-08-29 1999-10-05 Apple Computer, Inc. Method and system for avoiding starvation and deadlocks in a split-response interconnect of a computer system
WO1998015155A1 (de) 1996-09-30 1998-04-09 Siemens Aktiengesellschaft Verfahren zur mehrpunktverbindung in einem atm-übertragungssystem mit verbindungsindividuellen warteschlangen
JPH10154100A (ja) 1996-11-25 1998-06-09 Canon Inc 情報処理システム及び装置及びその制御方法
JP3904282B2 (ja) 1997-03-31 2007-04-11 株式会社ルネサステクノロジ 半導体集積回路装置
US6298370B1 (en) 1997-04-04 2001-10-02 Texas Instruments Incorporated Computer operating process allocating tasks between first and second processors at run time based upon current processor load
US6105119A (en) 1997-04-04 2000-08-15 Texas Instruments Incorporated Data transfer circuitry, DSP wrapper circuitry and improved processor devices, methods and systems
US6182201B1 (en) 1997-04-14 2001-01-30 International Business Machines Corporation Demand-based issuance of cache operations to a system bus
FR2762418B1 (fr) 1997-04-17 1999-06-11 Alsthom Cge Alcatel Procede de gestion d'une memoire partagee
US6072483A (en) * 1997-06-02 2000-06-06 Sony Corporation Active frame scroll interface
JP3524337B2 (ja) 1997-07-25 2004-05-10 キヤノン株式会社 バス管理装置及びそれを有する複合機器の制御装置
US6128728A (en) 1997-08-01 2000-10-03 Micron Technology, Inc. Virtual shadow registers and virtual register windows
US6085294A (en) 1997-10-24 2000-07-04 Compaq Computer Corporation Distributed data dependency stall mechanism
US6101420A (en) 1997-10-24 2000-08-08 Compaq Computer Corporation Method and apparatus for disambiguating change-to-dirty commands in a switch based multi-processing system with coarse directories
US6108752A (en) 1997-10-24 2000-08-22 Compaq Computer Corporation Method and apparatus for delaying victim writes in a switch-based multi-processor system to maintain data coherency
US6209065B1 (en) 1997-10-24 2001-03-27 Compaq Computer Corporation Mechanism for optimizing generation of commit-signals in a distributed shared-memory system
US6032228A (en) 1997-11-26 2000-02-29 International Business Machines Corporation Flexible cache-coherency mechanism
US6141733A (en) 1998-02-17 2000-10-31 International Business Machines Corporation Cache coherency protocol with independent implementation of optimized cache operations
US6289419B1 (en) 1998-03-06 2001-09-11 Sharp Kabushiki Kaisha Consistency control device merging updated memory blocks
US6070215A (en) 1998-03-13 2000-05-30 Compaq Computer Corporation Computer system with improved transition to low power operation
GB9806184D0 (en) 1998-03-23 1998-05-20 Sgs Thomson Microelectronics A cache coherency mechanism
US6185520B1 (en) 1998-05-22 2001-02-06 3Com Corporation Method and system for bus switching data transfers
US6195739B1 (en) 1998-06-29 2001-02-27 Cisco Technology, Inc. Method and apparatus for passing data among processor complex stages of a pipelined processing engine
US6266731B1 (en) 1998-09-03 2001-07-24 Compaq Computer Corporation High speed peripheral interconnect apparatus, method and system
US6338122B1 (en) * 1998-12-15 2002-01-08 International Business Machines Corporation Non-uniform memory access (NUMA) data processing system that speculatively forwards a read request to a remote processing node
US6631401B1 (en) 1998-12-21 2003-10-07 Advanced Micro Devices, Inc. Flexible probe/probe response routing for maintaining coherency
US6425060B1 (en) 1999-01-05 2002-07-23 International Business Machines Corporation Circuit arrangement and method with state-based transaction scheduling
US6681283B1 (en) * 1999-08-12 2004-01-20 Mips Technologies, Inc. Coherent data apparatus for an on-chip split transaction system bus
US6449701B1 (en) * 2000-09-20 2002-09-10 Broadcom Corporation Out of order associative queue in two clock domains
US7921188B2 (en) * 2001-08-16 2011-04-05 Newisys, Inc. Computer system partitioning using data transfer routing mechanism
US7394823B2 (en) * 2001-11-20 2008-07-01 Broadcom Corporation System having configurable interfaces for flexible system configurations
US6912602B2 (en) * 2001-11-20 2005-06-28 Broadcom Corporation System having two or more packet interfaces, a switch, and a shared packet DMA circuit
US7650412B2 (en) 2001-12-21 2010-01-19 Netapp, Inc. Systems and method of implementing disk ownership in networked storage

Also Published As

Publication number Publication date
EP1313024B1 (de) 2004-10-20
EP1313024A1 (de) 2003-05-21
DE60201650T2 (de) 2006-03-30
US7206879B2 (en) 2007-04-17
US7424561B2 (en) 2008-09-09
US20030105828A1 (en) 2003-06-05
DE60201650D1 (de) 2004-11-25
US20070214230A1 (en) 2007-09-13

Similar Documents

Publication Publication Date Title
ATE280413T1 (de) Systeme, welche eine mischung aus paketartigem, kohärentem und nicht-kohärentem verkehr verwenden,um die übertragung zwischen systemen zu optimieren
ATE291805T1 (de) Systeme, welche paketschnittstellen und paket-dma (direct memory access) schaltkreise beinhalten, um paketströme zu teilen und zusammenzusetzen
BR0010384A (pt) Aparelho e método para intercambiar dados de comprimento variável de acordo com o protocolo de enlace de rádio em sistema de comunicação móvel
DE69942113D1 (de) Bilderzeugungsgerät mit der Fähigkeit ,die Zeilenverarbeitungsgeschwindigkeit zu veränderen
NO20020142D0 (no) Sammenkoplingssystem i kompaktutförelse for komponenter innen signaloverföring
DE60203469D1 (de) System mit Schnittstellen und einem Schalter für die Trennung von kohärentem und nichtkohärentem Datenpaketverkehr
EP1315087A4 (de) Kommunikationsgerät und kommunikationsverfahren, netzwerksystem und robotervorrichtung
EP1422853A4 (de) Funkübertragungssystem und verfahren und in dem funkübertragungssystem verwendete sendestationsvorrichtung und empfangsstationsvorrichtung
WO2003067903A3 (en) Method and apparatus for band class acquisition and assignment in a wireless communication system
BR0010939A (pt) Sistemas e métodos para prover a caracterìstica de push to talk para sistemas de comunicação sem fio
EP1202593A4 (de) Kommunikationsentgerät und funkkommunikationsverfahren
BR9909953A (pt) Método e aparelho em um sistema de comunicação sem fio para dividir a funcionalidade de um browser entre um cliente sem fio e uma parte da infra-estrutura
DE69735351D1 (de) Netzwerkkommunikationssystem für bildinformationsübertragung zwischen bildverarbeitungsgeräten gemäss mehreren protokollen
DE69937386D1 (de) Übertragungssystem, Verfahren und Vorrichtung für Bandbreiteverwaltung
WO2004051908A3 (en) System and method for providing secure communication between network nodes
FI20012179A0 (fi) Tiedonsiirtomenetelmä ja -järjestelmä
EP1189428A3 (de) Bilderzeugungsvorrichtung
EP1587045A4 (de) Verkehrsinformationsbereitstellungssystem, verkehrsinformationsausdruckverfahren und -einrichtung
DE60123134D1 (de) Verfahren und vorrichtung für einen rekonfigurierbaren prozessor
EP1614249A4 (de) Signalübertragungsvorrichtung, stromversorgungssystem und serielle kommunikationsvorrichtung
DE60316909D1 (de) Verfahren zum Einrichten einer drahtlosen Nachrichtenverbindung
EP1466064A4 (de) Lamellensystem
EP1422880A4 (de) Netzwerkverbindungsvorrichtung, verbindungssystem und netzwerkverbindungsverfahren
EP1450534A4 (de) Datenübertragungssystem, datenübertragungsvorrichtung, datenempfangsvorrichtung und datenübertragungsverfahren
BR0312599A (pt) Métodos para estabelecer uma conexão de comunicação para tráfego entre um equipamento de usuário e uma rede e para estabelecer um contexto de pdp para tráfego de sinalização entre um equipamento de usuário e uma rede, produto de programa de computador, elemento de rede, sistema de comunicação, e, código de causa para um sistema de comunicação

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties