ATE295976T1 - Level 2 cache mit lokaler beibehaltung von kohärenzblöcken - Google Patents

Level 2 cache mit lokaler beibehaltung von kohärenzblöcken

Info

Publication number
ATE295976T1
ATE295976T1 AT02025692T AT02025692T ATE295976T1 AT E295976 T1 ATE295976 T1 AT E295976T1 AT 02025692 T AT02025692 T AT 02025692T AT 02025692 T AT02025692 T AT 02025692T AT E295976 T1 ATE295976 T1 AT E295976T1
Authority
AT
Austria
Prior art keywords
cache
node
level
local retention
coherence
Prior art date
Application number
AT02025692T
Other languages
English (en)
Inventor
Joseph B Rowlands
Original Assignee
Broadcom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Broadcom Corp filed Critical Broadcom Corp
Application granted granted Critical
Publication of ATE295976T1 publication Critical patent/ATE295976T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S707/00—Data processing: database and file management or data structures
    • Y10S707/99951—File or database maintenance
    • Y10S707/99952—Coherency, e.g. same view to multiple users

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Image Processing (AREA)
AT02025692T 2002-05-15 2002-11-20 Level 2 cache mit lokaler beibehaltung von kohärenzblöcken ATE295976T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US38074002P 2002-05-15 2002-05-15
US10/269,828 US6993631B2 (en) 2002-05-15 2002-10-11 L2 cache maintaining local ownership of remote coherency blocks

Publications (1)

Publication Number Publication Date
ATE295976T1 true ATE295976T1 (de) 2005-06-15

Family

ID=29272887

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02025692T ATE295976T1 (de) 2002-05-15 2002-11-20 Level 2 cache mit lokaler beibehaltung von kohärenzblöcken

Country Status (4)

Country Link
US (1) US6993631B2 (de)
EP (1) EP1363192B1 (de)
AT (1) ATE295976T1 (de)
DE (1) DE60204213T2 (de)

Families Citing this family (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7610305B2 (en) * 2003-04-24 2009-10-27 Sun Microsystems, Inc. Simultaneous global transaction and local transaction management in an application server
GB2403561A (en) * 2003-07-02 2005-01-05 Advanced Risc Mach Ltd Power control within a coherent multi-processor system
US7739252B2 (en) * 2003-07-14 2010-06-15 Oracle America, Inc. Read/write lock transaction manager freezing
US7093075B2 (en) * 2003-11-07 2006-08-15 International Business Machines Corporation Location-based placement algorithms for set associative cache memory
US7251710B1 (en) * 2004-01-12 2007-07-31 Advanced Micro Devices, Inc. Cache memory subsystem including a fixed latency R/W pipeline
US7818391B2 (en) 2004-01-20 2010-10-19 Hewlett-Packard Development Company, L.P. System and method to facilitate ordering point migration
US8090914B2 (en) * 2004-01-20 2012-01-03 Hewlett-Packard Development Company, L.P. System and method for creating ordering points
US20050160238A1 (en) * 2004-01-20 2005-07-21 Steely Simon C.Jr. System and method for conflict responses in a cache coherency protocol with ordering point migration
US8145847B2 (en) * 2004-01-20 2012-03-27 Hewlett-Packard Development Company, L.P. Cache coherency protocol with ordering points
US8468308B2 (en) * 2004-01-20 2013-06-18 Hewlett-Packard Development Company, L.P. System and method for non-migratory requests in a cache coherency protocol
US8176259B2 (en) * 2004-01-20 2012-05-08 Hewlett-Packard Development Company, L.P. System and method for resolving transactions in a cache coherency protocol
US7769959B2 (en) * 2004-01-20 2010-08-03 Hewlett-Packard Development Company, L.P. System and method to facilitate ordering point migration to memory
US7620696B2 (en) 2004-01-20 2009-11-17 Hewlett-Packard Development Company, L.P. System and method for conflict responses in a cache coherency protocol
JP4337591B2 (ja) * 2004-03-19 2009-09-30 株式会社日立製作所 情報処理装置、ネットワークシステムおよびネットワークシステムの制御方法
US8407424B2 (en) * 2005-11-07 2013-03-26 Silicon Graphics International Corp. Data coherence method and apparatus for multi-node computer system
US8275949B2 (en) * 2005-12-13 2012-09-25 International Business Machines Corporation System support storage and computer system
US7689771B2 (en) * 2006-09-19 2010-03-30 International Business Machines Corporation Coherency management of castouts
US11244727B2 (en) * 2006-11-29 2022-02-08 Rambus Inc. Dynamic memory rank configuration
US8401994B2 (en) 2009-09-18 2013-03-19 Oracle International Corporation Distributed consistent grid of in-memory database caches
US8306951B2 (en) 2009-09-18 2012-11-06 Oracle International Corporation Automated integrated high availability of the in-memory database cache and the backend enterprise database
US8019920B2 (en) * 2008-10-01 2011-09-13 Hewlett-Packard Development Company, L.P. Method to improve operating performance of a computing device
US8595425B2 (en) * 2009-09-25 2013-11-26 Nvidia Corporation Configurable cache for multiple clients
US9425978B2 (en) 2012-06-27 2016-08-23 Ubiquiti Networks, Inc. Method and apparatus for configuring and controlling interfacing devices
US10311154B2 (en) 2013-09-21 2019-06-04 Oracle International Corporation Combined row and columnar storage for in-memory databases for OLTP and analytics workloads
US9864816B2 (en) 2015-04-29 2018-01-09 Oracle International Corporation Dynamically updating data guide for hierarchical data objects
US11829349B2 (en) 2015-05-11 2023-11-28 Oracle International Corporation Direct-connect functionality in a distributed database grid
US10191944B2 (en) 2015-10-23 2019-01-29 Oracle International Corporation Columnar data arrangement for semi-structured data
US10803039B2 (en) 2017-05-26 2020-10-13 Oracle International Corporation Method for efficient primary key based queries using atomic RDMA reads on cache friendly in-memory hash index
US10719446B2 (en) 2017-08-31 2020-07-21 Oracle International Corporation Directly mapped buffer cache on non-volatile memory
US10956335B2 (en) 2017-09-29 2021-03-23 Oracle International Corporation Non-volatile cache access using RDMA
US11086876B2 (en) 2017-09-29 2021-08-10 Oracle International Corporation Storing derived summaries on persistent memory of a storage device
US10732836B2 (en) 2017-09-29 2020-08-04 Oracle International Corporation Remote one-sided persistent writes
US10802766B2 (en) 2017-09-29 2020-10-13 Oracle International Corporation Database with NVDIMM as persistent storage
US11675761B2 (en) 2017-09-30 2023-06-13 Oracle International Corporation Performing in-memory columnar analytic queries on externally resident data
US10592418B2 (en) * 2017-10-27 2020-03-17 Dell Products, L.P. Cache sharing in virtual clusters
US11170002B2 (en) 2018-10-19 2021-11-09 Oracle International Corporation Integrating Kafka data-in-motion with data-at-rest tables

Family Cites Families (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CH670715A5 (de) 1986-10-03 1989-06-30 Bbc Brown Boveri & Cie
US5765011A (en) * 1990-11-13 1998-06-09 International Business Machines Corporation Parallel processing system having a synchronous SIMD processing with processing elements emulating SIMD operation using individual instruction streams
US5963745A (en) * 1990-11-13 1999-10-05 International Business Machines Corporation APAP I/O programmable router
US5634004A (en) * 1994-05-16 1997-05-27 Network Programs, Inc. Directly programmable distribution element
EP0735487B1 (de) * 1995-03-31 2001-10-31 Sun Microsystems, Inc. Schnelle Zweitor-Cachesteuerungsschaltung für Datenprozessoren in einem paketvermittelten cachekohärenten Multiprozessorsystem
US5805920A (en) 1995-11-13 1998-09-08 Tandem Computers Incorporated Direct bulk data transfers
US5710907A (en) * 1995-12-22 1998-01-20 Sun Microsystems, Inc. Hybrid NUMA COMA caching system and methods for selecting between the caching modes
US5887138A (en) * 1996-07-01 1999-03-23 Sun Microsystems, Inc. Multiprocessing computer system employing local and global address spaces and COMA and NUMA access modes
US5878268A (en) * 1996-07-01 1999-03-02 Sun Microsystems, Inc. Multiprocessing system configured to store coherency state within multiple subnodes of a processing node
US5813029A (en) * 1996-07-09 1998-09-22 Micron Electronics, Inc. Upgradeable cache circuit using high speed multiplexer
US5961623A (en) * 1996-08-29 1999-10-05 Apple Computer, Inc. Method and system for avoiding starvation and deadlocks in a split-response interconnect of a computer system
JPH10154100A (ja) * 1996-11-25 1998-06-09 Canon Inc 情報処理システム及び装置及びその制御方法
JP3904282B2 (ja) * 1997-03-31 2007-04-11 株式会社ルネサステクノロジ 半導体集積回路装置
US6298370B1 (en) * 1997-04-04 2001-10-02 Texas Instruments Incorporated Computer operating process allocating tasks between first and second processors at run time based upon current processor load
US6105119A (en) * 1997-04-04 2000-08-15 Texas Instruments Incorporated Data transfer circuitry, DSP wrapper circuitry and improved processor devices, methods and systems
US6182201B1 (en) * 1997-04-14 2001-01-30 International Business Machines Corporation Demand-based issuance of cache operations to a system bus
FR2762418B1 (fr) * 1997-04-17 1999-06-11 Alsthom Cge Alcatel Procede de gestion d'une memoire partagee
JP3524337B2 (ja) 1997-07-25 2004-05-10 キヤノン株式会社 バス管理装置及びそれを有する複合機器の制御装置
US6085294A (en) * 1997-10-24 2000-07-04 Compaq Computer Corporation Distributed data dependency stall mechanism
US6209065B1 (en) * 1997-10-24 2001-03-27 Compaq Computer Corporation Mechanism for optimizing generation of commit-signals in a distributed shared-memory system
US6108752A (en) * 1997-10-24 2000-08-22 Compaq Computer Corporation Method and apparatus for delaying victim writes in a switch-based multi-processor system to maintain data coherency
US6101420A (en) * 1997-10-24 2000-08-08 Compaq Computer Corporation Method and apparatus for disambiguating change-to-dirty commands in a switch based multi-processing system with coarse directories
US6032228A (en) * 1997-11-26 2000-02-29 International Business Machines Corporation Flexible cache-coherency mechanism
US6141733A (en) 1998-02-17 2000-10-31 International Business Machines Corporation Cache coherency protocol with independent implementation of optimized cache operations
US6289419B1 (en) 1998-03-06 2001-09-11 Sharp Kabushiki Kaisha Consistency control device merging updated memory blocks
US6070215A (en) * 1998-03-13 2000-05-30 Compaq Computer Corporation Computer system with improved transition to low power operation
GB9806184D0 (en) 1998-03-23 1998-05-20 Sgs Thomson Microelectronics A cache coherency mechanism
US6195739B1 (en) * 1998-06-29 2001-02-27 Cisco Technology, Inc. Method and apparatus for passing data among processor complex stages of a pipelined processing engine
US6266731B1 (en) * 1998-09-03 2001-07-24 Compaq Computer Corporation High speed peripheral interconnect apparatus, method and system
US6546429B1 (en) * 1998-09-21 2003-04-08 International Business Machines Corporation Non-uniform memory access (NUMA) data processing system that holds and reissues requests at a target processing node in response to a retry
US6338122B1 (en) * 1998-12-15 2002-01-08 International Business Machines Corporation Non-uniform memory access (NUMA) data processing system that speculatively forwards a read request to a remote processing node
US6108764A (en) * 1998-12-17 2000-08-22 International Business Machines Corporation Non-uniform memory access (NUMA) data processing system with multiple caches concurrently holding data in a recent state from which data can be sourced by shared intervention
US6631401B1 (en) 1998-12-21 2003-10-07 Advanced Micro Devices, Inc. Flexible probe/probe response routing for maintaining coherency
US6425060B1 (en) 1999-01-05 2002-07-23 International Business Machines Corporation Circuit arrangement and method with state-based transaction scheduling
US6266743B1 (en) * 1999-02-26 2001-07-24 International Business Machines Corporation Method and system for providing an eviction protocol within a non-uniform memory access system
US6279085B1 (en) * 1999-02-26 2001-08-21 International Business Machines Corporation Method and system for avoiding livelocks due to colliding writebacks within a non-uniform memory access system
US6725343B2 (en) * 2000-10-05 2004-04-20 Hewlett-Packard Development Company, L.P. System and method for generating cache coherence directory entries and error correction codes in a multiprocessor system

Also Published As

Publication number Publication date
US6993631B2 (en) 2006-01-31
EP1363192B1 (de) 2005-05-18
DE60204213T2 (de) 2006-06-29
DE60204213D1 (de) 2005-06-23
US20030217236A1 (en) 2003-11-20
EP1363192A1 (de) 2003-11-19

Similar Documents

Publication Publication Date Title
ATE295976T1 (de) Level 2 cache mit lokaler beibehaltung von kohärenzblöcken
DE69432314D1 (de) Cachespeicher mit aufgeteiltem pegel
ES2137712T3 (es) Sistema temporalmente coherente de gestion en antememoria.
DE69616465D1 (de) Cachespeicher mit Datenvorausladung
DE68923863D1 (de) Ein-/Ausgabecachespeicherung.
HK1052239A1 (zh) 根據高速緩衝存儲一致性推斷的預載和預先佔有高速緩衝存儲行
DE69225970D1 (de) Substituierte 2-phenyl-3-methocypropensäurenester als fungizide mittel.
DE69131734D1 (de) Datenprozessor mit verschachteltem DRAM-Speicher
DE60234975D1 (de) Navigationssystem mit dezentralisierter Architektur
DE69210714D1 (de) Durch Doppelzweck-On-Chip-Speicher implementierter Echtzeit-Cachespeicher
ATE158882T1 (de) Vorrichtung zur echten lru-ersetzung
ATE526631T1 (de) Verfahren und vorrichtungen zur proaktiven speicherverwaltung
DE60219436D1 (de) System mit adressbasierter Intraknotenkohärenz und datenbasierter Interknotenkohärenz
ATE197101T1 (de) System, architektur und verfahren mit hoher leistung für einen universellen multiport dynamischen direktzugriffspeicher mit internem cache-speicher
WO2005001693A3 (en) Multiprocessor system with dynamic cache coherency regions
DE69129913D1 (de) Datenprozessor mit aufgeschobenem Laden eines Cache-Speichers
DE69114434D1 (de) Plattenspeichergerät.
DE69120982D1 (de) Datenspeicher mit Cache-Speicher und Verfahren dafür
DE69229667D1 (de) Simulierte cachespeicher-assoziativität
EP0589658A3 (de) Einblenden von graphischen Daten mit Speicherung der graphischen Parameter.
ES2090315T5 (es) Medio de contraste que contiene un agente de contraste no ionico y sales de sodio y de calcio.
FI914295A0 (fi) Nya skvalensyntetasinhibitorer.
WO2003083663A3 (en) Use of context identifiers in cache memory
DE69021192D1 (de) Peripheres Massenspeichersubsystem.
DE69019493D1 (de) Optische Halbleiterspeicheranordnung für optische Datenspeicherung mit erhöhter Speicherdichte.

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties