ATE297019T1 - Kalibrierung von einseitig abgeschlossenen kanälen zur erzielung differentielles signal- niveau - Google Patents

Kalibrierung von einseitig abgeschlossenen kanälen zur erzielung differentielles signal- niveau

Info

Publication number
ATE297019T1
ATE297019T1 AT01996100T AT01996100T ATE297019T1 AT E297019 T1 ATE297019 T1 AT E297019T1 AT 01996100 T AT01996100 T AT 01996100T AT 01996100 T AT01996100 T AT 01996100T AT E297019 T1 ATE297019 T1 AT E297019T1
Authority
AT
Austria
Prior art keywords
driver circuits
measurement circuit
signals
dut
circuits
Prior art date
Application number
AT01996100T
Other languages
English (en)
Inventor
Sean P Adam
William J Bowhers
Original Assignee
Teradyne Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Teradyne Inc filed Critical Teradyne Inc
Application granted granted Critical
Publication of ATE297019T1 publication Critical patent/ATE297019T1/de

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/08—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Amplifiers (AREA)
AT01996100T 2000-12-12 2001-12-03 Kalibrierung von einseitig abgeschlossenen kanälen zur erzielung differentielles signal- niveau ATE297019T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/735,261 US6675117B2 (en) 2000-12-12 2000-12-12 Calibrating single ended channels for differential performance
PCT/US2001/046390 WO2002048727A2 (en) 2000-12-12 2001-12-03 Calibrating single ended channels for obtaining differential performance level

Publications (1)

Publication Number Publication Date
ATE297019T1 true ATE297019T1 (de) 2005-06-15

Family

ID=24955022

Family Applications (1)

Application Number Title Priority Date Filing Date
AT01996100T ATE297019T1 (de) 2000-12-12 2001-12-03 Kalibrierung von einseitig abgeschlossenen kanälen zur erzielung differentielles signal- niveau

Country Status (11)

Country Link
US (1) US6675117B2 (de)
EP (1) EP1344073B1 (de)
JP (1) JP4255284B2 (de)
KR (1) KR100813869B1 (de)
CN (1) CN1248003C (de)
AT (1) ATE297019T1 (de)
AU (1) AU2002227211A1 (de)
DE (1) DE60111263T2 (de)
MY (1) MY131077A (de)
TW (1) TW519711B (de)
WO (1) WO2002048727A2 (de)

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JP2002074988A (ja) * 2000-08-28 2002-03-15 Mitsubishi Electric Corp 半導体装置および半導体装置のテスト方法
US6993695B2 (en) * 2001-06-06 2006-01-31 Agilent Technologies, Inc. Method and apparatus for testing digital devices using transition timestamps
US7231306B1 (en) * 2002-04-30 2007-06-12 Rambus Inc. Method and apparatus for calibrating static timing offsets across multiple outputs
US7210059B2 (en) * 2003-08-19 2007-04-24 Micron Technology, Inc. System and method for on-board diagnostics of memory modules
US7072355B2 (en) * 2003-08-21 2006-07-04 Rambus, Inc. Periodic interface calibration for high speed communication
US7310752B2 (en) 2003-09-12 2007-12-18 Micron Technology, Inc. System and method for on-board timing margin testing of memory modules
US7120743B2 (en) 2003-10-20 2006-10-10 Micron Technology, Inc. Arbitration system and method for memory responses in a hub-based memory system
US7216196B2 (en) * 2003-12-29 2007-05-08 Micron Technology, Inc. Memory hub and method for memory system performance monitoring
US7158536B2 (en) * 2004-01-28 2007-01-02 Rambus Inc. Adaptive-allocation of I/O bandwidth using a configurable interconnect topology
US7400670B2 (en) 2004-01-28 2008-07-15 Rambus, Inc. Periodic calibration for communication channels by drift tracking
US8422568B2 (en) 2004-01-28 2013-04-16 Rambus Inc. Communication channel calibration for drift conditions
US7095789B2 (en) 2004-01-28 2006-08-22 Rambus, Inc. Communication channel calibration for drift conditions
US6961862B2 (en) * 2004-03-17 2005-11-01 Rambus, Inc. Drift tracking feedback for communication channels
KR100594268B1 (ko) * 2004-04-02 2006-06-30 삼성전자주식회사 싱글-엔드 신호들을 시리얼 병합하여 분석하는 측정 회로및 그 방법
US7978754B2 (en) * 2004-05-28 2011-07-12 Rambus Inc. Communication channel calibration with nonvolatile parameter store for recovery
US7310748B2 (en) * 2004-06-04 2007-12-18 Micron Technology, Inc. Memory hub tester interface and method for use thereof
US7516029B2 (en) 2004-06-09 2009-04-07 Rambus, Inc. Communication channel calibration using feedback
US7535958B2 (en) * 2004-06-14 2009-05-19 Rambus, Inc. Hybrid wired and wireless chip-to-chip communications
US7489739B2 (en) * 2004-09-17 2009-02-10 Rambus, Inc. Method and apparatus for data recovery
US7362107B2 (en) * 2005-11-08 2008-04-22 Mediatek Inc. Systems and methods for automatically eliminating imbalance between signals
KR100780952B1 (ko) * 2006-06-27 2007-12-03 삼성전자주식회사 디스큐 장치 및 방법, 그리고 이를 이용한 데이터 수신장치및 방법
US7925005B2 (en) * 2006-10-23 2011-04-12 Silicon Laboratories, Inc. Longitudinal balance calibration for a subscriber line interface circuit
JP2009071533A (ja) 2007-09-12 2009-04-02 Advantest Corp 差動信号伝送装置および試験装置
KR20100068670A (ko) * 2008-12-15 2010-06-24 삼성전자주식회사 채널 스큐 보상 기능을 갖는 인터페이스 회로, 이를 구비한통신 시스템 및 채널 스큐 보상 방법
KR20110095913A (ko) * 2009-01-28 2011-08-25 가부시키가이샤 어드밴티스트 시험 장치 및 시험 방법
TWI445969B (zh) * 2010-01-12 2014-07-21 Hon Hai Prec Ind Co Ltd 低壓差分訊號測試系統及方法
KR101789077B1 (ko) * 2010-02-23 2017-11-20 삼성전자주식회사 온-다이 터미네이션 회로, 데이터 출력 버퍼, 반도체 메모리 장치, 메모리 모듈, 온-다이 터미네이션 회로의 구동 방법, 데이터 출력 버퍼의 구동 방법 및 온-다이 터미네이션 트레이닝 방법
WO2012060017A1 (ja) 2010-11-05 2012-05-10 富士通株式会社 送受信装置および情報処理装置
US9910129B1 (en) * 2013-09-20 2018-03-06 Marvell International Ltd. Method and apparatus for calibrating transmit delay and receive delay
US10180340B2 (en) * 2014-10-09 2019-01-15 Invensense, Inc. System and method for MEMS sensor system synchronization
CN107390113A (zh) * 2017-08-16 2017-11-24 上海华岭集成电路技术股份有限公司 一种ate测试差分信号电平的方法
US10401391B1 (en) 2018-02-26 2019-09-03 Samsung Display Co., Ltd. Low overhead on chip scope
US11221361B2 (en) 2019-09-03 2022-01-11 Teradyne, Inc. Controlling power dissipation in an output stage of a test channel

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4660197A (en) 1985-11-01 1987-04-21 Teradyne, Inc. Circuitry for synchronizing a multiple channel circuit tester
US5058087A (en) 1987-05-29 1991-10-15 Siemens Aktiengesellschaft Process for determining the electrical duration of signal paths
US4947113A (en) 1989-03-31 1990-08-07 Hewlett-Packard Company Driver circuit for providing pulses having clean edges
US5661427A (en) 1994-10-05 1997-08-26 Micro Linear Corporation Series terminated clock deskewing apparatus
EP0815461B1 (de) 1995-03-16 2000-06-21 Teradyne, Inc. Zeitgeber mit mehreren kohärenten synchronisierten takten
US5982827A (en) 1997-05-14 1999-11-09 Hewlett-Packard Co. Means for virtual deskewing of high/intermediate/low DUT data
US6133725A (en) 1998-03-26 2000-10-17 Teradyne, Inc. Compensating for the effects of round-trip delay in automatic test equipment
JP2000009801A (ja) * 1998-06-19 2000-01-14 Advantest Corp Ｉｃ試験装置のｔｄｒタイミング校正方法
US6052810A (en) * 1998-07-07 2000-04-18 Ltx Corporation Differential driver circuit for use in automatic test equipment
US6281699B1 (en) * 2000-03-15 2001-08-28 Teradyne, Inc. Detector with common mode comparator for automatic test equipment

Also Published As

Publication number Publication date
EP1344073B1 (de) 2005-06-01
US20020072870A1 (en) 2002-06-13
DE60111263T2 (de) 2006-04-27
CN1486432A (zh) 2004-03-31
AU2002227211A1 (en) 2002-06-24
US6675117B2 (en) 2004-01-06
TW519711B (en) 2003-02-01
DE60111263D1 (de) 2005-07-07
WO2002048727A2 (en) 2002-06-20
EP1344073A2 (de) 2003-09-17
JP4255284B2 (ja) 2009-04-15
WO2002048727A3 (en) 2003-04-17
KR20030063417A (ko) 2003-07-28
CN1248003C (zh) 2006-03-29
MY131077A (en) 2007-07-31
KR100813869B1 (ko) 2008-03-17
JP2004515788A (ja) 2004-05-27

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