ATE310274T1 - System und methode zur anpassung der kommunikation über signalleitungen - Google Patents

System und methode zur anpassung der kommunikation über signalleitungen

Info

Publication number
ATE310274T1
ATE310274T1 AT02256425T AT02256425T ATE310274T1 AT E310274 T1 ATE310274 T1 AT E310274T1 AT 02256425 T AT02256425 T AT 02256425T AT 02256425 T AT02256425 T AT 02256425T AT E310274 T1 ATE310274 T1 AT E310274T1
Authority
AT
Austria
Prior art keywords
signal lines
parameters
over
storage mechanism
receiver
Prior art date
Application number
AT02256425T
Other languages
English (en)
Inventor
Brian L Smith
Jue Wu
Jyh-Ming Jong
Wai Fong
Leo Yuan
Prabhansu Chakrabarti
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Application granted granted Critical
Publication of ATE310274T1 publication Critical patent/ATE310274T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/24—Marginal checking or other specified testing methods not covered by G06F11/26, e.g. race tests
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H1/00—Details of emergency protective circuit arrangements
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
    • H02H7/26—Sectionalised protection of cable or line systems, e.g. for disconnecting a section on which a short-circuit, earth fault, or arc discharge has occured
    • H02H7/267—Sectionalised protection of cable or line systems, e.g. for disconnecting a section on which a short-circuit, earth fault, or arc discharge has occured for parallel lines and wires
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
    • H02H3/38—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to both voltage and current; responsive to phase angle between voltage and current
    • H02H3/385—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to both voltage and current; responsive to phase angle between voltage and current using at least one homopolar quantity

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Dc Digital Transmission (AREA)
  • Communication Control (AREA)
AT02256425T 2001-09-13 2002-09-13 System und methode zur anpassung der kommunikation über signalleitungen ATE310274T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/951,928 US6944692B2 (en) 2001-09-13 2001-09-13 Automated calibration of I/O over a multi-variable eye window

Publications (1)

Publication Number Publication Date
ATE310274T1 true ATE310274T1 (de) 2005-12-15

Family

ID=25492348

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02256425T ATE310274T1 (de) 2001-09-13 2002-09-13 System und methode zur anpassung der kommunikation über signalleitungen

Country Status (6)

Country Link
US (2) US6944692B2 (de)
EP (1) EP1300749B1 (de)
JP (1) JP2003218961A (de)
KR (1) KR20030023541A (de)
AT (1) ATE310274T1 (de)
DE (1) DE60207356T2 (de)

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US7526498B2 (en) 2001-09-14 2009-04-28 Siemens Communications, Inc. Method for generating data structures for automatically testing GUI applications
US6948152B2 (en) * 2001-09-14 2005-09-20 Siemens Communications, Inc. Data structures for use with environment based data driven automated test engine for GUI applications
US7076401B2 (en) * 2002-04-30 2006-07-11 Intel Corporation Method and apparatus for measuring data timing using unity time-voltage sawtooth ramps
EP1394559A1 (de) * 2002-08-27 2004-03-03 Siemens Aktiengesellschaft Verfahren und Anordnung zur Erkennung und Behebung von Leitungsdefekten
TW583405B (en) * 2002-12-23 2004-04-11 Via Tech Inc Signal detection method suitable for integrated circuit chip
JP4155088B2 (ja) * 2003-04-18 2008-09-24 日本電気株式会社 情報処理装置
US7168027B2 (en) * 2003-06-12 2007-01-23 Micron Technology, Inc. Dynamic synchronization of data capture on an optical or other high speed communications link
US7190931B2 (en) * 2003-09-29 2007-03-13 Intel Corporation Receiver calibration apparatus, method, and system
US20060020412A1 (en) * 2004-07-23 2006-01-26 Bruensteiner Matthew M Analog waveform information from binary sampled measurements
US7685333B2 (en) * 2005-03-22 2010-03-23 Sigmatel, Inc Method and system for communicating with memory devices utilizing selected timing parameters from a timing table
US7483477B2 (en) * 2005-04-27 2009-01-27 Agilent Technologies, Inc. User interface for selection of sampling parameters in a logic analyzer whose data receivers are in groups each having a separate threshold that is common to the channels within each group
US7362836B2 (en) * 2005-04-27 2008-04-22 Agilent Technologies, Inc. Method for selecting optimum sampling parameters for a plurality of data receivers having at least one sampling parameter in common
JP4648095B2 (ja) * 2005-06-02 2011-03-09 アラクサラネットワークス株式会社 信号伝送回路およびその調整方法
KR100712519B1 (ko) * 2005-07-25 2007-04-27 삼성전자주식회사 아이 마스크를 이용하여 회로의 특성을 검출하는 테스트장비 및 테스트 방법
JP4437986B2 (ja) * 2005-09-30 2010-03-24 富士通マイクロエレクトロニクス株式会社 半導体集積回路装置、インターフェース試験制御回路および試験方法
US7822110B1 (en) 2005-10-04 2010-10-26 Oracle America, Inc. Eye diagram determination during system operation
US8271231B2 (en) * 2005-10-26 2012-09-18 Hewlett-Packard Development Company, L.P. Computer device configuration system and method
US20070121496A1 (en) * 2005-11-30 2007-05-31 Sinykin Joshua P System and method for amplitude optimization in high-speed serial transmissions
US20070186131A1 (en) * 2006-02-06 2007-08-09 Texas Instruments Incorporated Low cost imbedded load board diagnostic test fixture
JP4670676B2 (ja) * 2006-02-17 2011-04-13 日本電気株式会社 スイッチ及びネットワークブリッジ装置
US20070220737A1 (en) * 2006-03-17 2007-09-27 Anthony Stoughton Integrated circuit test result communication
US7307560B2 (en) * 2006-04-28 2007-12-11 Rambus Inc. Phase linearity test circuit
US7925164B2 (en) * 2006-08-30 2011-04-12 Broadlight Ltd. Method and system for power management control in passive optical networks
US20080275662A1 (en) * 2007-05-01 2008-11-06 Vladimir Dmitriev-Zdorov Generating transmission-code compliant test sequences
US8190804B1 (en) * 2009-03-12 2012-05-29 Sonics, Inc. Various methods and apparatus for a memory scheduler with an arbiter
US20120017118A1 (en) * 2010-07-19 2012-01-19 Advanced Micro Devices, Inc. Method and apparatus for testing an integrated circuit including an i/o interface
US8711906B2 (en) * 2010-11-08 2014-04-29 Lsi Corporation Tracking data eye operating margin for steady state adaptation
JP6372202B2 (ja) * 2014-07-07 2018-08-15 ソニー株式会社 受信装置、送信装置、および通信システム
KR102173881B1 (ko) * 2015-04-10 2020-11-04 에스케이하이닉스 주식회사 스큐 제거 동작을 수행하는 반도체 장치
US9665298B2 (en) * 2015-04-21 2017-05-30 Sandisk Technologies Llc Method and system to reduce power usage on an I/O interface
US11119151B2 (en) * 2019-12-02 2021-09-14 Rohde & Schwarz Gmbh & Co. Kg Method for identifying and compensating for systems errors
JP2024074199A (ja) * 2022-11-18 2024-05-30 ルネサスエレクトロニクス株式会社 半導体装置および遅延制御方法
TWI849668B (zh) * 2023-01-03 2024-07-21 威鋒電子股份有限公司 積體電路、測試系統及其操作方法

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JPH06148279A (ja) * 1992-10-30 1994-05-27 Yokogawa Hewlett Packard Ltd 電子デバイス試験・測定装置、およびそのタイミングならびに電圧レベル校正方法
US5978742A (en) * 1997-04-04 1999-11-02 Tektronix, Inc. Method and apparatus for digital sampling of electrical waveforms
JP3429977B2 (ja) 1997-05-16 2003-07-28 富士通株式会社 スキュー低減回路及び半導体装置
US6028451A (en) * 1997-12-31 2000-02-22 Intel Corporation Method and apparatus for topology dependent slew rate control
US6160851A (en) * 1998-02-26 2000-12-12 National Semiconductor Corporation Line driver calibration circuit
US6041419A (en) 1998-05-27 2000-03-21 S3 Incorporated Programmable delay timing calibrator for high speed data interface
US6560716B1 (en) 1999-11-10 2003-05-06 Lsi Logic Corporation System for measuring delay of digital signal using clock generator and delay unit wherein a set of digital elements of clock generator identical to a set of digital elements of delay unit
US6622103B1 (en) * 2000-06-20 2003-09-16 Formfactor, Inc. System for calibrating timing of an integrated circuit wafer tester
US6622107B1 (en) 2000-08-25 2003-09-16 Nptest Llc Edge placement and jitter measurement for electronic elements
US6546343B1 (en) 2000-11-13 2003-04-08 Rambus, Inc. Bus line current calibration
US6684350B1 (en) * 2000-12-22 2004-01-27 Cisco Technology, Inc. Repetitive pattern testing circuit for AC-coupled systems
US6326830B1 (en) 2000-12-29 2001-12-04 Intel Corporation Automatic clock calibration circuit

Also Published As

Publication number Publication date
US7296104B2 (en) 2007-11-13
JP2003218961A (ja) 2003-07-31
DE60207356D1 (de) 2005-12-22
EP1300749A1 (de) 2003-04-09
US6944692B2 (en) 2005-09-13
KR20030023541A (ko) 2003-03-19
EP1300749B1 (de) 2005-11-16
DE60207356T2 (de) 2006-08-03
US20030051086A1 (en) 2003-03-13
US20060009931A1 (en) 2006-01-12

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