ATE322742T1 - Verfahren zum kontrollieren der kristallinen orientierung einer verbundstruktur - Google Patents

Verfahren zum kontrollieren der kristallinen orientierung einer verbundstruktur

Info

Publication number
ATE322742T1
ATE322742T1 AT02748966T AT02748966T ATE322742T1 AT E322742 T1 ATE322742 T1 AT E322742T1 AT 02748966 T AT02748966 T AT 02748966T AT 02748966 T AT02748966 T AT 02748966T AT E322742 T1 ATE322742 T1 AT E322742T1
Authority
AT
Austria
Prior art keywords
orientation
secondary structures
controlling
crystalline orientation
composite structure
Prior art date
Application number
AT02748966T
Other languages
English (en)
Inventor
Franck Fournel
Bernard Aspar
Hubert Moriceau
Original Assignee
Commissariat Energie Atomique
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat Energie Atomique filed Critical Commissariat Energie Atomique
Application granted granted Critical
Publication of ATE322742T1 publication Critical patent/ATE322742T1/de

Links

Classifications

    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
    • C30B33/06—Joining of crystals
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices
    • H10P10/12—Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/24—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement by concurrent transfer of multiple parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/201—Marks applied to devices, e.g. for alignment or identification located on the periphery of wafers, e.g. orientation notches or lot numbers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/501—Marks applied to devices, e.g. for alignment or identification for use before dicing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S117/00—Single-crystal, oriented-crystal, and epitaxy growth processes; non-coating apparatus therefor
    • Y10S117/901—Levitation, reduced gravity, microgravity, space
    • Y10S117/902—Specified orientation, shape, crystallography, or size of seed or substrate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24355—Continuous and nonuniform or irregular surface on layer or component [e.g., roofing, etc.]
    • Y10T428/24372—Particulate matter
    • Y10T428/24421—Silicon containing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/31504—Composite [nonstructural laminate]
    • Y10T428/31551—Of polyamidoester [polyurethane, polyisocyanate, polycarbamate, etc.]
    • Y10T428/31645—Next to addition polymer from unsaturated monomers

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Analysing Materials By The Use Of Radiation (AREA)
  • Laminated Bodies (AREA)
  • Optical Filters (AREA)
  • Casting Or Compression Moulding Of Plastics Or The Like (AREA)
  • Compositions Of Oxide Ceramics (AREA)
  • Inorganic Compounds Of Heavy Metals (AREA)
  • Recrystallisation Techniques (AREA)
AT02748966T 2001-06-22 2002-06-20 Verfahren zum kontrollieren der kristallinen orientierung einer verbundstruktur ATE322742T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0108257A FR2826378B1 (fr) 2001-06-22 2001-06-22 Structure composite a orientation cristalline uniforme et procede de controle de l'orientation cristalline d'une telle structure

Publications (1)

Publication Number Publication Date
ATE322742T1 true ATE322742T1 (de) 2006-04-15

Family

ID=8864655

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02748966T ATE322742T1 (de) 2001-06-22 2002-06-20 Verfahren zum kontrollieren der kristallinen orientierung einer verbundstruktur

Country Status (7)

Country Link
US (1) US7258743B2 (de)
EP (1) EP1397835B1 (de)
JP (1) JP4357957B2 (de)
AT (1) ATE322742T1 (de)
DE (1) DE60210452T2 (de)
FR (1) FR2826378B1 (de)
WO (1) WO2003005443A2 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004119943A (ja) * 2002-09-30 2004-04-15 Renesas Technology Corp 半導体ウェハおよびその製造方法
WO2005010245A1 (en) * 2003-07-30 2005-02-03 Element Six Limited Method of manufacturing diamond substrates
GB0317854D0 (en) * 2003-07-30 2003-09-03 Element Six Ltd Method of manufacturing diamond substrates
FR2877662B1 (fr) * 2004-11-09 2007-03-02 Commissariat Energie Atomique Reseau de particules et procede de realisation d'un tel reseau.
FR2881264B1 (fr) 2005-01-21 2007-06-01 Commissariat Energie Atomique Monochromateur a rayon x ou a neutrons
US7674687B2 (en) * 2005-07-27 2010-03-09 Silicon Genesis Corporation Method and structure for fabricating multiple tiled regions onto a plate using a controlled cleaving process
US8389099B1 (en) 2007-06-01 2013-03-05 Rubicon Technology, Inc. Asymmetrical wafer configurations and method for creating the same
US8348720B1 (en) 2007-06-19 2013-01-08 Rubicon Technology, Inc. Ultra-flat, high throughput wafer lapping process
FR2939151A1 (fr) * 2008-12-01 2010-06-04 Soitec Silicon On Insulator Lingots formes d'au moins deux lingots elementaires, un procede de fabrication et une plaquette qui en est issue
US7927975B2 (en) 2009-02-04 2011-04-19 Micron Technology, Inc. Semiconductor material manufacture
CN102379024A (zh) * 2009-11-13 2012-03-14 住友电气工业株式会社 制造半导体衬底的方法
US20120003823A1 (en) * 2009-11-13 2012-01-05 Sumitomo Electric Industries, Ltd. Method for manufacturing semiconductor substrate
WO2011058830A1 (ja) * 2009-11-13 2011-05-19 住友電気工業株式会社 半導体基板の製造方法
JP2015079830A (ja) * 2013-10-16 2015-04-23 三菱電機株式会社 光半導体装置、光半導体装置の製造方法、及び光モジュールの製造方法
US11204549B2 (en) * 2018-10-26 2021-12-21 Canon Kabushiki Kaisha Superstrate with an offset mesa and methods of using the same
FR3105876B1 (fr) * 2019-12-30 2021-11-26 Soitec Silicon On Insulator Procédé de fabrication d’une structure composite comprenant une couche mince en SiC monocristallin sur un substrat support

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61155815A (ja) 1984-12-28 1986-07-15 Toshiba Corp 記録計
JPS61158152A (ja) * 1984-12-28 1986-07-17 Toshiba Corp 圧接型半導体装置
JPH0952184A (ja) * 1995-08-14 1997-02-25 Natl Res Inst For Metals 単結晶積層材
FR2781082B1 (fr) * 1998-07-10 2002-09-20 Commissariat Energie Atomique Structure semiconductrice en couche mince comportant une couche de repartition de chaleur
US20020089016A1 (en) 1998-07-10 2002-07-11 Jean-Pierre Joly Thin layer semi-conductor structure comprising a heat distribution layer
JP3324553B2 (ja) * 1999-03-30 2002-09-17 日本電気株式会社 半導体装置の製造方法及び位置合わせ方法
AU5522300A (en) * 1999-06-28 2001-01-31 Mikroelektronik Centret (Mic) Nanometer-scale modulation
AU2049801A (en) * 1999-12-09 2001-06-18 Cornell Research Foundation Inc. Fabrication of periodic surface structures with nanometer-scale spacings

Also Published As

Publication number Publication date
WO2003005443A3 (fr) 2003-10-16
US7258743B2 (en) 2007-08-21
WO2003005443A2 (fr) 2003-01-16
FR2826378B1 (fr) 2004-10-15
JP4357957B2 (ja) 2009-11-04
FR2826378A1 (fr) 2002-12-27
EP1397835A2 (de) 2004-03-17
JP2004521518A (ja) 2004-07-15
EP1397835B1 (de) 2006-04-05
DE60210452D1 (de) 2006-05-18
DE60210452T2 (de) 2006-11-09
US20030175531A1 (en) 2003-09-18

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