ATE326726T1 - Datenstruktur zur datenübertragung auf einem zeitlich gemultiplexten bus - Google Patents

Datenstruktur zur datenübertragung auf einem zeitlich gemultiplexten bus

Info

Publication number
ATE326726T1
ATE326726T1 AT02778527T AT02778527T ATE326726T1 AT E326726 T1 ATE326726 T1 AT E326726T1 AT 02778527 T AT02778527 T AT 02778527T AT 02778527 T AT02778527 T AT 02778527T AT E326726 T1 ATE326726 T1 AT E326726T1
Authority
AT
Austria
Prior art keywords
data
data structure
time
bus
multiplexed bus
Prior art date
Application number
AT02778527T
Other languages
English (en)
Inventor
Echartea Jesus Callej Palomino
Bugambilias
Guillermo Lopez
Shiro Suzuki
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of ATE326726T1 publication Critical patent/ATE326726T1/de

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks
    • H04L12/28Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40Bus networks
    • H04L12/40006Architecture of a communication node
    • H04L12/40032Details regarding a bus interface enhancer
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/90Buffering arrangements
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/90Buffering arrangements
    • H04L49/9023Buffering arrangements for implementing a jitter-buffer
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q2213/00Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/1305Software aspects
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q2213/00Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13103Memory
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q2213/00Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13106Microprocessor, CPU
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q2213/00Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13166Fault prevention
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q2213/00Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13174Data transmission, file transfer
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q2213/00Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13204Protocols
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q2213/00Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13214Clock signals
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q2213/00Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13292Time division multiplexing, TDM
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q2213/00Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13299Bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Small-Scale Networks (AREA)
  • Communication Control (AREA)
AT02778527T 2001-10-15 2002-10-11 Datenstruktur zur datenübertragung auf einem zeitlich gemultiplexten bus ATE326726T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/978,620 US6748506B2 (en) 2001-10-15 2001-10-15 Bus frame protocol

Publications (1)

Publication Number Publication Date
ATE326726T1 true ATE326726T1 (de) 2006-06-15

Family

ID=25526274

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02778527T ATE326726T1 (de) 2001-10-15 2002-10-11 Datenstruktur zur datenübertragung auf einem zeitlich gemultiplexten bus

Country Status (8)

Country Link
US (1) US6748506B2 (de)
EP (1) EP1451697B1 (de)
CN (1) CN1582435A (de)
AT (1) ATE326726T1 (de)
CA (1) CA2462650A1 (de)
DE (1) DE60211550D1 (de)
TW (1) TW591399B (de)
WO (1) WO2003034244A1 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7690621B2 (en) * 2003-04-15 2010-04-06 Board Of Trustees Operating Michigan State University Prestrained thin-film shape memory actuator using polymeric substrates
US7724762B2 (en) * 2007-06-25 2010-05-25 Texas Instruments Incorporated Efficient transmission of packets within a network communication device
WO2010059150A1 (en) * 2008-11-19 2010-05-27 Lsi Corporation Interconnects using self-timed time-division multiplexed bus
DE102015120242B3 (de) * 2015-11-23 2017-02-09 Beckhoff Automation Gmbh Verfahren zum Betreiben eines Kommunikationsnetzwerkes, Kommunikationsnetzwerk, Steuervorrichtung und Datenverarbeitungsvorrichtung

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4546429A (en) * 1984-12-27 1985-10-08 The United States Of America As Represented By The Secretary Of The Air Force Interactive communication channel
FR2625054B1 (fr) 1987-12-18 1990-05-04 Trt Telecom Radio Electr Dispositif de transformation de paquets de donnees en un multiplex regulier pour systeme de transmission utilisant le principe d'a.m.r.t.
US5351236A (en) * 1992-10-20 1994-09-27 At&T Bell Laboratories Multirate, sonet-ready, switching arrangement
US6467003B1 (en) * 1997-01-21 2002-10-15 Honeywell International, Inc. Fault tolerant data communication network
US5926629A (en) * 1997-02-18 1999-07-20 Advanced Micro Devices, Inc. Continuously operating interconnection bus
US5970240A (en) * 1997-06-25 1999-10-19 Quickturn Design Systems, Inc. Method and apparatus for configurable memory emulation
US6154465A (en) 1998-10-06 2000-11-28 Vertical Networks, Inc. Systems and methods for multiple mode voice and data communications using intelligenty bridged TDM and packet buses and methods for performing telephony and data functions using the same
US20030012214A1 (en) * 2001-07-09 2003-01-16 Nortel Networks Limited Hybrid time switch as a rotator tandem

Also Published As

Publication number Publication date
TW591399B (en) 2004-06-11
US6748506B2 (en) 2004-06-08
US20030074503A1 (en) 2003-04-17
DE60211550D1 (de) 2006-06-22
CN1582435A (zh) 2005-02-16
EP1451697B1 (de) 2006-05-17
CA2462650A1 (en) 2003-04-24
WO2003034244A1 (en) 2003-04-24
EP1451697A1 (de) 2004-09-01

Similar Documents

Publication Publication Date Title
BRPI0512808A (pt) computação eficiente de matrizes de filtro espacial para diversidade de transmissão de direcionamento em um sistema de comunicação mimo
TW200502851A (en) Microprocessor including a first level cache and a second level cache having different cache line sizes
WO2004046885A3 (en) Reconfiguration of content for display on devices of different types
CN104598194A (zh) 一种头尾指针链表存储器的初始化方法及电路
EP1665056A4 (de) Mehrprozessorsystem und -verfahren mit mehreren speicher-hub-modulen
ATE266223T1 (de) Aus blöcken zusammengesetzte flüssigkristallanzeige
CN105528347B (zh) 数据块储存方法、数据查询方法和数据修改方法
EP2224415A3 (de) Kartendatenprodukt und Kartendatenverarbeitungseinrichtung
DE602004007402D1 (de) Effiziente verbindung zwischen modulen wechselbarer elektronischer schaltungskarten
GB2353122A (en) Method and apparatus for asynchronously updating a mirror of a source device
WO2007038225A3 (en) A memory module including a plurality of integrated circuit memory devices and a plurality of buffer devices in a matrix topology
ATE372542T1 (de) Zugriff zum breiten speicher
WO2004057461A3 (en) Data division method and device using exclusive or calculation
MY148787A (en) Matrix display having addressable display elements and methods
BR0302968A (pt) Intercalador e método de intercalação em um sistema de comunicação
TW200519731A (en) Method, system, and program for constructing a packet
TW200519735A (en) Data element size control within parallel lanes of processing
TW200736942A (en) Parallel multi-rate circuit simulation
ATE326726T1 (de) Datenstruktur zur datenübertragung auf einem zeitlich gemultiplexten bus
AU2003259191A8 (en) Method, system, and program for memory based data transfer
ATE323999T1 (de) System und verfahren zum verbinden von rahmendaten durch das einfügen von bestimmungsfeldern in steuerblöcke
AU2001288553A1 (en) Method and apparatus for connecting a massively parallel processor array to a memory array in a bit serial manner
AU2003292534A1 (en) Method and system for simulating communications networks, object and computer program product therefor
GB2382674B (en) Data access in a processor
TW200506603A (en) Memory management in a data processing system

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties