ATE329354T1 - STRUCTURED MEMORY CELL TEST - Google Patents

STRUCTURED MEMORY CELL TEST

Info

Publication number
ATE329354T1
ATE329354T1 AT02717602T AT02717602T ATE329354T1 AT E329354 T1 ATE329354 T1 AT E329354T1 AT 02717602 T AT02717602 T AT 02717602T AT 02717602 T AT02717602 T AT 02717602T AT E329354 T1 ATE329354 T1 AT E329354T1
Authority
AT
Austria
Prior art keywords
memory cell
cell test
structured memory
bit lines
memory cells
Prior art date
Application number
AT02717602T
Other languages
German (de)
Inventor
Michael Tripp
Tak Mak
Michael Spica
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of ATE329354T1 publication Critical patent/ATE329354T1/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C2029/5004—Voltage

Landscapes

  • Tests Of Electronic Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Micro-Organisms Or Cultivation Processes Thereof (AREA)
  • Measuring Or Testing Involving Enzymes Or Micro-Organisms (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)

Abstract

An apparatus and method for testing memory cells comprising coupling a first and a second memory cell to a first and a second bit lines, respectively, reading data from the first and second memory cells through the first and second bit lines, and comparing the voltage levels of the first and second bit lines.
AT02717602T 2001-03-30 2002-03-08 STRUCTURED MEMORY CELL TEST ATE329354T1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/823,642 US6757209B2 (en) 2001-03-30 2001-03-30 Memory cell structural test

Publications (1)

Publication Number Publication Date
ATE329354T1 true ATE329354T1 (en) 2006-06-15

Family

ID=25239313

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02717602T ATE329354T1 (en) 2001-03-30 2002-03-08 STRUCTURED MEMORY CELL TEST

Country Status (9)

Country Link
US (1) US6757209B2 (en)
EP (1) EP1374250B1 (en)
JP (1) JP2004530243A (en)
KR (1) KR100544362B1 (en)
CN (1) CN100538910C (en)
AT (1) ATE329354T1 (en)
DE (1) DE60212103T2 (en)
MY (1) MY127555A (en)
WO (1) WO2002080183A2 (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7480195B2 (en) * 2005-05-11 2009-01-20 Micron Technology, Inc. Internal data comparison for memory testing
US7602778B2 (en) * 2005-06-29 2009-10-13 Cisco Technology, Inc. System and methods for compressing message headers
JP4773791B2 (en) * 2005-09-30 2011-09-14 富士通セミコンダクター株式会社 Semiconductor memory device and memory test circuit
US7548473B2 (en) * 2006-04-14 2009-06-16 Purdue Research Foundation Apparatus and methods for determining memory device faults
CN101714407B (en) * 2009-11-12 2012-08-08 钰创科技股份有限公司 Row address reserved storage location trigger circuit and row address reserved storage location device
JP6430194B2 (en) * 2014-09-29 2018-11-28 ルネサスエレクトロニクス株式会社 Semiconductor memory device
CN108051767B (en) * 2018-01-04 2019-07-19 南京国睿安泰信科技股份有限公司 A kind of automatic diagnosis method for integrated circuit tester
KR20240111461A (en) * 2023-01-10 2024-07-17 삼성전자주식회사 Memory cell array of static random access memory and static random access memory including the same

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JPS57105897A (en) * 1980-12-23 1982-07-01 Fujitsu Ltd Semiconductor storage device
US4503536A (en) 1982-09-13 1985-03-05 General Dynamics Digital circuit unit testing system utilizing signature analysis
US4527272A (en) 1982-12-06 1985-07-02 Tektronix, Inc. Signature analysis using random probing and signature memory
JPS61261895A (en) * 1985-05-16 1986-11-19 Toshiba Corp Semiconductor memory device
JPS61292300A (en) * 1985-06-18 1986-12-23 Toshiba Corp Facilitating circuit for on-chip memory test
JP2523586B2 (en) * 1987-02-27 1996-08-14 株式会社日立製作所 Semiconductor memory device
JP2831767B2 (en) * 1990-01-10 1998-12-02 株式会社アドバンテスト Semiconductor memory test equipment
JPH04212799A (en) * 1990-01-31 1992-08-04 Nec Ic Microcomput Syst Ltd Semiconductor memory built in test circuit
JPH04211160A (en) * 1990-03-20 1992-08-03 Mitsubishi Electric Corp Semiconductor memory
KR940007240B1 (en) * 1992-02-21 1994-08-10 현대전자산업 주식회사 Parallel test circuit
JP3251637B2 (en) * 1992-05-06 2002-01-28 株式会社東芝 Semiconductor storage device
JP3307473B2 (en) * 1992-09-09 2002-07-24 ソニー エレクトロニクス インコーポレイテッド Test circuit for semiconductor memory
JPH07211099A (en) * 1994-01-12 1995-08-11 Sony Corp Semiconductor memory device tester
JPH07307100A (en) * 1994-05-11 1995-11-21 Nec Corp Memory integrated circuit
US5708598A (en) * 1995-04-24 1998-01-13 Saito; Tamio System and method for reading multiple voltage level memories
JP3607407B2 (en) * 1995-04-26 2005-01-05 株式会社日立製作所 Semiconductor memory device
US5973967A (en) * 1997-01-03 1999-10-26 Programmable Microelectronics Corporation Page buffer having negative voltage level shifter
US6002623A (en) * 1997-02-12 1999-12-14 Micron Technology, Inc. Semiconductor memory with test circuit
JPH10308100A (en) 1997-05-06 1998-11-17 Mitsubishi Electric Corp Semiconductor storage device
KR100269319B1 (en) 1997-12-29 2000-10-16 윤종용 Semiconductor memory device including simultaneous enabling circuit for column select line and control method
US5963497A (en) * 1998-05-18 1999-10-05 Silicon Aquarius, Inc. Dynamic random access memory system with simultaneous access and refresh operations and methods for using the same
KR100308191B1 (en) 1998-05-28 2001-11-30 윤종용 Semiconductor memory device having built-in parallel test circuit
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US6353568B1 (en) * 2000-12-29 2002-03-05 Lsi Logic Corporation Dual threshold voltage sense amplifier

Also Published As

Publication number Publication date
EP1374250B1 (en) 2006-06-07
US20020141259A1 (en) 2002-10-03
DE60212103T2 (en) 2007-01-04
KR100544362B1 (en) 2006-01-23
JP2004530243A (en) 2004-09-30
CN1537312A (en) 2004-10-13
WO2002080183A2 (en) 2002-10-10
EP1374250A2 (en) 2004-01-02
CN100538910C (en) 2009-09-09
MY127555A (en) 2006-12-29
US6757209B2 (en) 2004-06-29
WO2002080183A3 (en) 2003-04-17
KR20030085084A (en) 2003-11-01
DE60212103D1 (en) 2006-07-20
HK1060437A1 (en) 2004-08-06

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Legal Events

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