ATE337652T1 - Einrichtung zum austausch von datensignalen zwischen zwei taktbereichen - Google Patents

Einrichtung zum austausch von datensignalen zwischen zwei taktbereichen

Info

Publication number
ATE337652T1
ATE337652T1 AT03809396T AT03809396T ATE337652T1 AT E337652 T1 ATE337652 T1 AT E337652T1 AT 03809396 T AT03809396 T AT 03809396T AT 03809396 T AT03809396 T AT 03809396T AT E337652 T1 ATE337652 T1 AT E337652T1
Authority
AT
Austria
Prior art keywords
data signals
exchanging data
memory element
clock areas
clock
Prior art date
Application number
AT03809396T
Other languages
English (en)
Inventor
Groot Hermana W H De
Der Tuijn Roland M M H Van
Original Assignee
Koninkl Philips Electronics Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv filed Critical Koninkl Philips Electronics Nv
Application granted granted Critical
Publication of ATE337652T1 publication Critical patent/ATE337652T1/de

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M9/00—Parallel/series conversion or vice versa
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L2007/045—Fill bit or bits, idle words

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Communication Control (AREA)
  • Information Transfer Systems (AREA)
AT03809396T 2002-10-25 2003-10-06 Einrichtung zum austausch von datensignalen zwischen zwei taktbereichen ATE337652T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP02079466 2002-10-25

Publications (1)

Publication Number Publication Date
ATE337652T1 true ATE337652T1 (de) 2006-09-15

Family

ID=32116294

Family Applications (1)

Application Number Title Priority Date Filing Date
AT03809396T ATE337652T1 (de) 2002-10-25 2003-10-06 Einrichtung zum austausch von datensignalen zwischen zwei taktbereichen

Country Status (7)

Country Link
EP (1) EP1559235B1 (de)
JP (1) JP2006504313A (de)
CN (1) CN100505615C (de)
AT (1) ATE337652T1 (de)
AU (1) AU2003264777A1 (de)
DE (1) DE60307876T2 (de)
WO (1) WO2004038994A1 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7971115B2 (en) 2009-01-31 2011-06-28 Xilinx, Inc. Method and apparatus for detecting and correcting errors in a parallel to serial circuit
WO2015131350A1 (zh) 2014-03-05 2015-09-11 华为技术有限公司 时钟同步方法、设备及通信系统
CN113517894B (zh) * 2021-07-14 2022-07-08 上海安路信息科技股份有限公司 串并转换电路

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4323521A1 (de) * 1993-07-14 1995-01-19 Sel Alcatel Ag Verfahren zum Umsetzen eines parallelisierten, zeitlich gemultiplexten Datenstroms in einzelne serielle Datenströme und umgekehrt, sowie Umsetzer dafür
US5508967A (en) * 1993-08-09 1996-04-16 Matsushita Electric Industrial Co., Ltd. Line memory
US5619506A (en) * 1995-04-27 1997-04-08 Adtran, Inc. Method and apparatus for reducing waiting time jitter in pulse stuffing synchronized digital communications
US5926120A (en) * 1996-03-28 1999-07-20 National Semiconductor Corporation Multi-channel parallel to serial and serial to parallel conversion using a RAM array
SE506817C2 (sv) * 1996-06-20 1998-02-16 Ericsson Telefon Ab L M Seriell-parallell- och parallell-seriellomvandlare innefattande frekvensdelare
US5909563A (en) * 1996-09-25 1999-06-01 Philips Electronics North America Corporation Computer system including an interface for transferring data between two clock domains
US5915128A (en) * 1997-01-29 1999-06-22 Unisys Corporation Serial speed-matching buffer utilizing plurality of registers where each register selectively receives data from transferring units or sequentially transfers data to another register
US6128319A (en) * 1997-11-24 2000-10-03 Network Excellence For Enterprises Corp. Hybrid interface for packet data switching
US6215727B1 (en) * 2000-04-04 2001-04-10 Intel Corporation Method and apparatus for utilizing parallel memory in a serial memory system

Also Published As

Publication number Publication date
EP1559235A1 (de) 2005-08-03
CN100505615C (zh) 2009-06-24
DE60307876T2 (de) 2007-04-05
JP2006504313A (ja) 2006-02-02
DE60307876D1 (de) 2006-10-05
EP1559235B1 (de) 2006-08-23
WO2004038994A1 (en) 2004-05-06
CN1706142A (zh) 2005-12-07
AU2003264777A1 (en) 2004-05-13

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Legal Events

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