ATE339006T1 - Pufferanordnung für speicher - Google Patents

Pufferanordnung für speicher

Info

Publication number
ATE339006T1
ATE339006T1 AT03731546T AT03731546T ATE339006T1 AT E339006 T1 ATE339006 T1 AT E339006T1 AT 03731546 T AT03731546 T AT 03731546T AT 03731546 T AT03731546 T AT 03731546T AT E339006 T1 ATE339006 T1 AT E339006T1
Authority
AT
Austria
Prior art keywords
memory
devices
storage
buffer
buffer arrangement
Prior art date
Application number
AT03731546T
Other languages
English (en)
Inventor
Narendra Khandekar
James Dodd
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of ATE339006T1 publication Critical patent/ATE339006T1/de

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store

Landscapes

  • Memory System (AREA)
  • Dram (AREA)
  • Read Only Memory (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Information Transfer Systems (AREA)
  • Oscillators With Electromechanical Resonators (AREA)
  • Vehicle Body Suspensions (AREA)
  • Non-Volatile Memory (AREA)
AT03731546T 2002-06-27 2003-05-22 Pufferanordnung für speicher ATE339006T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/186,357 US6639820B1 (en) 2002-06-27 2002-06-27 Memory buffer arrangement

Publications (1)

Publication Number Publication Date
ATE339006T1 true ATE339006T1 (de) 2006-09-15

Family

ID=29250181

Family Applications (1)

Application Number Title Priority Date Filing Date
AT03731546T ATE339006T1 (de) 2002-06-27 2003-05-22 Pufferanordnung für speicher

Country Status (9)

Country Link
US (1) US6639820B1 (de)
EP (1) EP1516339B1 (de)
KR (1) KR100647162B1 (de)
CN (1) CN1679108B (de)
AT (1) ATE339006T1 (de)
AU (1) AU2003240534A1 (de)
DE (1) DE60308183T2 (de)
TW (1) TWI290322B (de)
WO (1) WO2004003916A1 (de)

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US8335894B1 (en) 2008-07-25 2012-12-18 Google Inc. Configurable memory system with interface circuit
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US8327104B2 (en) 2006-07-31 2012-12-04 Google Inc. Adjusting the timing of signals associated with a memory system
US8796830B1 (en) 2006-09-01 2014-08-05 Google Inc. Stackable low-profile lead frame package
US8111566B1 (en) 2007-11-16 2012-02-07 Google, Inc. Optimal channel design for memory devices for providing a high-speed memory interface
US8130560B1 (en) 2006-11-13 2012-03-06 Google Inc. Multi-rank partial width memory modules
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US7392338B2 (en) 2006-07-31 2008-06-24 Metaram, Inc. Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits
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US9507739B2 (en) 2005-06-24 2016-11-29 Google Inc. Configurable memory circuit system and method
US10013371B2 (en) 2005-06-24 2018-07-03 Google Llc Configurable memory circuit system and method
US9542352B2 (en) 2006-02-09 2017-01-10 Google Inc. System and method for reducing command scheduling constraints of memory circuits
US8089795B2 (en) 2006-02-09 2012-01-03 Google Inc. Memory module with memory stack and interface with enhanced capabilities
US20080082763A1 (en) 2006-10-02 2008-04-03 Metaram, Inc. Apparatus and method for power management of memory circuits by a system or component thereof
US7590796B2 (en) * 2006-07-31 2009-09-15 Metaram, Inc. System and method for power management in memory systems
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US7930492B2 (en) * 2005-09-12 2011-04-19 Samsung Electronics Co., Ltd. Memory system having low power consumption
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Also Published As

Publication number Publication date
DE60308183D1 (de) 2006-10-19
CN1679108B (zh) 2011-08-17
CN1679108A (zh) 2005-10-05
TW200407904A (en) 2004-05-16
KR100647162B1 (ko) 2006-11-23
AU2003240534A1 (en) 2004-01-19
EP1516339A1 (de) 2005-03-23
TWI290322B (en) 2007-11-21
DE60308183T2 (de) 2007-08-23
US6639820B1 (en) 2003-10-28
KR20050012832A (ko) 2005-02-02
WO2004003916A1 (en) 2004-01-08
EP1516339B1 (de) 2006-09-06

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Legal Events

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