ATE344487T1 - Reduzierung von komponenten in einer montgomery multiplikations-recheneinheit - Google Patents

Reduzierung von komponenten in einer montgomery multiplikations-recheneinheit

Info

Publication number
ATE344487T1
ATE344487T1 AT02761642T AT02761642T ATE344487T1 AT E344487 T1 ATE344487 T1 AT E344487T1 AT 02761642 T AT02761642 T AT 02761642T AT 02761642 T AT02761642 T AT 02761642T AT E344487 T1 ATE344487 T1 AT E344487T1
Authority
AT
Austria
Prior art keywords
montgomery multiplication
chain
montgomery
multiplication unit
initial parameter
Prior art date
Application number
AT02761642T
Other languages
English (en)
Inventor
Mike Ruehle
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of ATE344487T1 publication Critical patent/ATE344487T1/de

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
    • G06F7/728—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic using Montgomery reduction

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Complex Calculations (AREA)
  • Executing Machine-Instructions (AREA)
  • Photoreceptors In Electrophotography (AREA)
  • Image Generation (AREA)
  • Apparatus For Radiation Diagnosis (AREA)
  • Diaphragms For Electromechanical Transducers (AREA)
  • Television Systems (AREA)
  • Logic Circuits (AREA)
AT02761642T 2001-09-28 2002-09-13 Reduzierung von komponenten in einer montgomery multiplikations-recheneinheit ATE344487T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/966,044 US6625631B2 (en) 2001-09-28 2001-09-28 Component reduction in montgomery multiplier processing element

Publications (1)

Publication Number Publication Date
ATE344487T1 true ATE344487T1 (de) 2006-11-15

Family

ID=25510848

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02761642T ATE344487T1 (de) 2001-09-28 2002-09-13 Reduzierung von komponenten in einer montgomery multiplikations-recheneinheit

Country Status (7)

Country Link
US (1) US6625631B2 (de)
EP (1) EP1430392B1 (de)
CN (1) CN100356317C (de)
AT (1) ATE344487T1 (de)
DE (1) DE60215835T2 (de)
TW (1) TWI244614B (de)
WO (1) WO2003029956A1 (de)

Families Citing this family (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7266725B2 (en) 2001-09-03 2007-09-04 Pact Xpp Technologies Ag Method for debugging reconfigurable architectures
DE19654595A1 (de) 1996-12-20 1998-07-02 Pact Inf Tech Gmbh I0- und Speicherbussystem für DFPs sowie Bausteinen mit zwei- oder mehrdimensionaler programmierbaren Zellstrukturen
US6542998B1 (en) 1997-02-08 2003-04-01 Pact Gmbh Method of self-synchronization of configurable elements of a programmable module
US8686549B2 (en) * 2001-09-03 2014-04-01 Martin Vorbach Reconfigurable elements
DE19861088A1 (de) 1997-12-22 2000-02-10 Pact Inf Tech Gmbh Verfahren zur Reparatur von integrierten Schaltkreisen
JP2003505753A (ja) * 1999-06-10 2003-02-12 ペーアーツェーテー インフォルマツィオーンステヒノロギー ゲゼルシャフト ミット ベシュレンクテル ハフツング セル構造におけるシーケンス分割方法
DE50115584D1 (de) 2000-06-13 2010-09-16 Krass Maren Pipeline ct-protokolle und -kommunikation
US9626325B2 (en) * 2000-10-06 2017-04-18 Pact Xpp Technologies Ag Array processor having a segmented bus system
US8058899B2 (en) 2000-10-06 2011-11-15 Martin Vorbach Logic cell array and bus system
US6804696B2 (en) * 2000-12-19 2004-10-12 International Business Machines Corporation Pipelining operations in a system for performing modular multiplication
US7844796B2 (en) 2001-03-05 2010-11-30 Martin Vorbach Data processing device and method
US7444531B2 (en) 2001-03-05 2008-10-28 Pact Xpp Technologies Ag Methods and devices for treating and processing data
JP3950638B2 (ja) * 2001-03-05 2007-08-01 株式会社日立製作所 耐タンパーモジュラ演算処理方法
US9037807B2 (en) 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
US7996827B2 (en) 2001-08-16 2011-08-09 Martin Vorbach Method for the translation of programs for reconfigurable architectures
US7434191B2 (en) 2001-09-03 2008-10-07 Pact Xpp Technologies Ag Router
US8686475B2 (en) * 2001-09-19 2014-04-01 Pact Xpp Technologies Ag Reconfigurable elements
US20030065696A1 (en) * 2001-09-28 2003-04-03 Ruehle Michael D. Method and apparatus for performing modular exponentiation
US6922717B2 (en) * 2001-09-28 2005-07-26 Intel Corporation Method and apparatus for performing modular multiplication
WO2003060747A2 (de) 2002-01-19 2003-07-24 Pact Xpp Technologies Ag Reconfigurierbarer prozessor
US8914590B2 (en) 2002-08-07 2014-12-16 Pact Xpp Technologies Ag Data processing method and device
US20110161977A1 (en) * 2002-03-21 2011-06-30 Martin Vorbach Method and device for data processing
AU2003286131A1 (en) 2002-08-07 2004-03-19 Pact Xpp Technologies Ag Method and device for processing data
US7394284B2 (en) 2002-09-06 2008-07-01 Pact Xpp Technologies Ag Reconfigurable sequencer structure
US7010561B2 (en) * 2002-10-09 2006-03-07 William L. Freking Systolic ring-planarized cylindrical array modular multipler
JP4700611B2 (ja) * 2003-08-28 2011-06-15 ペーアーツェーテー イクスペーペー テクノロジーズ アクチエンゲゼルシャフト データ処理装置およびデータ処理方法
US20060140399A1 (en) * 2004-12-28 2006-06-29 Young David W Pre-calculation mechanism for signature decryption
US7873830B2 (en) * 2006-01-13 2011-01-18 International Business Machines Corporation Methods for coordinating access to memory from at least two cryptography secure processing units
JP2009524134A (ja) 2006-01-18 2009-06-25 ペーアーツェーテー イクスペーペー テクノロジーズ アクチエンゲゼルシャフト ハードウェア定義方法
EP2220554A1 (de) * 2007-11-17 2010-08-25 Krass, Maren Rekonfiguri erbare fliesskomma- und bit- ebenen datenverarbeitungseinheit
WO2009068014A2 (de) * 2007-11-28 2009-06-04 Pact Xpp Technologies Ag Über datenverarbeitung
WO2009071329A1 (en) * 2007-12-07 2009-06-11 Pact Xpp Technologies Ag Using function calls as compiler directives
US8560814B2 (en) 2010-05-04 2013-10-15 Oracle International Corporation Thread fairness on a multi-threaded processor with multi-cycle cryptographic operations
US8583902B2 (en) 2010-05-07 2013-11-12 Oracle International Corporation Instruction support for performing montgomery multiplication
US9430191B2 (en) * 2013-11-08 2016-08-30 Micron Technology, Inc. Division operations for memory
CN109947393B (zh) * 2017-12-20 2021-11-02 航天信息股份有限公司 基于求余器的运算方法及装置
CN109284085B (zh) * 2018-09-25 2023-03-31 国网湖南省电力有限公司 一种基于fpga的高速模乘和模幂运算方法及装置
TWI798640B (zh) * 2021-02-09 2023-04-11 新唐科技股份有限公司 常數乘法器
CN114510450B (zh) * 2021-05-25 2024-11-26 无锡沐创集成电路设计有限公司 加密算法的加速计算方法、装置和阵列单元算子系统
US12500736B2 (en) * 2023-08-14 2025-12-16 Microsoft Technology Licensing, Llc Montgomery multiplier architecture
CN117234458B (zh) * 2023-11-09 2024-02-23 深圳大普微电子股份有限公司 乘法阵列、数据处理方法、处理终端及存储介质

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB8815868D0 (en) * 1988-07-04 1988-08-10 British Aerospace Digital signal processing
US6061706A (en) * 1997-10-10 2000-05-09 United Microelectronics Corp. Systolic linear-array modular multiplier with pipeline processing elements
US6763365B2 (en) * 2000-12-19 2004-07-13 International Business Machines Corporation Hardware implementation for modular multiplication using a plurality of almost entirely identical processor elements

Also Published As

Publication number Publication date
HK1063325A1 (en) 2004-12-24
US20030065695A1 (en) 2003-04-03
DE60215835T2 (de) 2007-06-21
WO2003029956A1 (en) 2003-04-10
TWI244614B (en) 2005-12-01
EP1430392A1 (de) 2004-06-23
DE60215835D1 (de) 2006-12-14
CN1561479A (zh) 2005-01-05
CN100356317C (zh) 2007-12-19
EP1430392B1 (de) 2006-11-02
US6625631B2 (en) 2003-09-23

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