ATE346342T1 - Datenverarbeitungsvorrichtung mit adressenumlenkung als reaktion auf periodische adressenmuster - Google Patents

Datenverarbeitungsvorrichtung mit adressenumlenkung als reaktion auf periodische adressenmuster

Info

Publication number
ATE346342T1
ATE346342T1 AT03810543T AT03810543T ATE346342T1 AT E346342 T1 ATE346342 T1 AT E346342T1 AT 03810543 T AT03810543 T AT 03810543T AT 03810543 T AT03810543 T AT 03810543T AT E346342 T1 ATE346342 T1 AT E346342T1
Authority
AT
Austria
Prior art keywords
address
addresses
processing units
data processing
output
Prior art date
Application number
AT03810543T
Other languages
English (en)
Inventor
Bijo Thomas
Original Assignee
Koninkl Philips Electronics Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv filed Critical Koninkl Philips Electronics Nv
Application granted granted Critical
Publication of ATE346342T1 publication Critical patent/ATE346342T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1626—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests
    • G06F13/1631—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests through address comparison
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System (AREA)
  • Communication Control (AREA)
  • Storage Device Security (AREA)
  • Computer And Data Communications (AREA)
  • Small-Scale Networks (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Debugging And Monitoring (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
AT03810543T 2002-11-05 2003-10-08 Datenverarbeitungsvorrichtung mit adressenumlenkung als reaktion auf periodische adressenmuster ATE346342T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP02079612 2002-11-05

Publications (1)

Publication Number Publication Date
ATE346342T1 true ATE346342T1 (de) 2006-12-15

Family

ID=32309402

Family Applications (1)

Application Number Title Priority Date Filing Date
AT03810543T ATE346342T1 (de) 2002-11-05 2003-10-08 Datenverarbeitungsvorrichtung mit adressenumlenkung als reaktion auf periodische adressenmuster

Country Status (9)

Country Link
US (1) US20060041692A1 (de)
EP (1) EP1563401B1 (de)
JP (1) JP2006505845A (de)
CN (1) CN1711528A (de)
AT (1) ATE346342T1 (de)
AU (1) AU2003264788A1 (de)
DE (1) DE60309923T2 (de)
TW (1) TW200416553A (de)
WO (1) WO2004042591A1 (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100583072C (zh) * 2006-10-13 2010-01-20 鸿富锦精密工业（深圳）有限公司 控制器、地址控制方法及使用其的总线数据传输系统

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5835627A (ja) * 1981-08-26 1983-03-02 Toshiba Corp メモリデ−タ先取り制御方式
JPS62206658A (ja) * 1986-03-07 1987-09-11 Hitachi Ltd 記憶管理装置
US4933846A (en) * 1987-04-24 1990-06-12 Network Systems Corporation Network communications adapter with dual interleaved memory banks servicing multiple processors
US4920484A (en) * 1988-10-05 1990-04-24 Yale University Multiprocessor/memory interconnection network wherein messages sent through the network to the same memory are combined
JP3203701B2 (ja) * 1990-11-01 2001-08-27 インターナショナル・ビジネス・マシーンズ・コーポレーション コードセグメントのリンク方法とそのシステム及びコードセグメントのダイナミックリンク方法
US5551054A (en) * 1991-11-19 1996-08-27 Adaptec, Inc. Page mode buffer controller for transferring Nb byte pages between a host and buffer memory without interruption except for refresh
JP3178909B2 (ja) * 1992-01-10 2001-06-25 株式会社東芝 半導体メモリ装置
JPH0619785A (ja) * 1992-03-27 1994-01-28 Matsushita Electric Ind Co Ltd 分散共有仮想メモリーとその構成方法
US5519839A (en) * 1992-10-02 1996-05-21 Compaq Computer Corp. Double buffering operations between the memory bus and the expansion bus of a computer system
US5777628A (en) * 1996-05-29 1998-07-07 Hewlett-Packard Company Method and apparatus for detecting cache collisions in a two dimensional memory
US5884050A (en) * 1996-06-21 1999-03-16 Digital Equipment Corporation Mechanism for high bandwidth DMA transfers in a PCI environment
US6170046B1 (en) * 1997-10-28 2001-01-02 Mmc Networks, Inc. Accessing a memory system via a data or address bus that provides access to more than one part
US7433948B2 (en) * 2002-01-23 2008-10-07 Cisco Technology, Inc. Methods and apparatus for implementing virtualization of storage within a storage area network
US6816989B2 (en) * 2001-12-28 2004-11-09 Hewlett-Packard Development Company, L.P. Method and apparatus for efficiently managing bandwidth of a debug data output port or buffer
US7617329B2 (en) * 2002-12-30 2009-11-10 Intel Corporation Programmable protocol to support coherent and non-coherent transactions in a multinode system

Also Published As

Publication number Publication date
EP1563401B1 (de) 2006-11-22
EP1563401A1 (de) 2005-08-17
US20060041692A1 (en) 2006-02-23
CN1711528A (zh) 2005-12-21
WO2004042591A1 (en) 2004-05-21
JP2006505845A (ja) 2006-02-16
TW200416553A (en) 2004-09-01
AU2003264788A1 (en) 2004-06-07
DE60309923D1 (de) 2007-01-04
DE60309923T2 (de) 2007-10-18

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Legal Events

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