ATE346380T1 - Verfahren zur musterbildung - Google Patents

Verfahren zur musterbildung

Info

Publication number
ATE346380T1
ATE346380T1 AT01933947T AT01933947T ATE346380T1 AT E346380 T1 ATE346380 T1 AT E346380T1 AT 01933947 T AT01933947 T AT 01933947T AT 01933947 T AT01933947 T AT 01933947T AT E346380 T1 ATE346380 T1 AT E346380T1
Authority
AT
Austria
Prior art keywords
pattern formation
film
mocr
ito film
etched
Prior art date
Application number
AT01933947T
Other languages
English (en)
Inventor
Yoshihisa Hatta
Original Assignee
Koninkl Philips Electronics Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv filed Critical Koninkl Philips Electronics Nv
Application granted granted Critical
Publication of ATE346380T1 publication Critical patent/ATE346380T1/de

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0314Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral top-gate TFTs comprising only a single gate
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/6729Thin-film transistors [TFT] characterised by the electrodes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/6729Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00Etching of wafers, substrates or parts of devices
    • H10P50/20Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/26Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
    • H10P50/264Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
    • H10P50/266Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00Etching of wafers, substrates or parts of devices
    • H10P50/60Wet etching
    • H10P50/66Wet etching of conductive or resistive materials
    • H10P50/663Wet etching of conductive or resistive materials by chemical means only
    • H10P50/667Wet etching of conductive or resistive materials by chemical means only by liquid etching only

Landscapes

  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)
  • Drying Of Semiconductors (AREA)
  • Weting (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrically Operated Instructional Devices (AREA)
  • Diaphragms For Electromechanical Transducers (AREA)
  • Oscillators With Electromechanical Resonators (AREA)
AT01933947T 2000-05-23 2001-05-08 Verfahren zur musterbildung ATE346380T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000151234A JP4630420B2 (ja) 2000-05-23 2000-05-23 パターン形成方法

Publications (1)

Publication Number Publication Date
ATE346380T1 true ATE346380T1 (de) 2006-12-15

Family

ID=18656826

Family Applications (1)

Application Number Title Priority Date Filing Date
AT01933947T ATE346380T1 (de) 2000-05-23 2001-05-08 Verfahren zur musterbildung

Country Status (8)

Country Link
US (2) US6693000B2 (de)
EP (1) EP1290723B1 (de)
JP (1) JP4630420B2 (de)
KR (1) KR100765305B1 (de)
CN (1) CN100429754C (de)
AT (1) ATE346380T1 (de)
DE (1) DE60124704T2 (de)
WO (1) WO2001091172A2 (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE60336441D1 (de) 2002-09-02 2011-05-05 Samsung Electronics Co Ltd Kontaktstruktur für eine Halbleitervorrichtung, dünnschichtige Transistoranordnung mit einer solchen Kontaktstruktur und dessen Herstellungsmethode
JP2005223049A (ja) * 2004-02-04 2005-08-18 Ricoh Co Ltd 半導体装置、半導体装置の製造方法、および表示装置
JP2005223048A (ja) * 2004-02-04 2005-08-18 Ricoh Co Ltd 半導体装置、半導体装置の製造方法、および表示装置
US7547627B2 (en) * 2004-11-29 2009-06-16 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US7560735B2 (en) 2005-04-22 2009-07-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor element, organic transistor, light-emitting device, and electronic device
JP5121162B2 (ja) * 2005-04-22 2013-01-16 株式会社半導体エネルギー研究所 半導体素子、発光装置及び電気機器
WO2007043493A1 (en) 2005-10-14 2007-04-19 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US8149346B2 (en) 2005-10-14 2012-04-03 Semiconductor Energy Laboratory Co., Ltd. Display device and manufacturing method thereof
JP5082385B2 (ja) * 2006-11-01 2012-11-28 セイコーエプソン株式会社 電気光学装置の製造方法
GB2448174B (en) * 2007-04-04 2009-12-09 Cambridge Display Tech Ltd Organic thin film transistors
US9082857B2 (en) 2008-09-01 2015-07-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device comprising an oxide semiconductor layer
CN102742014B (zh) * 2010-01-22 2015-06-24 株式会社半导体能源研究所 半导体装置
CN102763202B (zh) * 2010-02-19 2016-08-03 株式会社半导体能源研究所 半导体装置及其制造方法
CN103477441B (zh) 2011-04-18 2016-05-18 夏普株式会社 薄膜晶体管、显示面板和薄膜晶体管的制造方法
KR101960796B1 (ko) * 2012-03-08 2019-07-16 삼성디스플레이 주식회사 박막 트랜지스터의 제조 방법, 표시 기판의 제조 방법 및 표시 기판
CN102629671B (zh) * 2012-04-25 2015-05-06 上海大学 硅基微显示器的有机电致发光器件制备方法
KR102039102B1 (ko) * 2012-12-24 2019-11-01 삼성디스플레이 주식회사 박막 트랜지스터 표시판 및 그 제조 방법
JP2016219452A (ja) * 2015-05-14 2016-12-22 富士通株式会社 多層基板及び多層基板の製造方法
CN107196619B (zh) * 2017-05-04 2023-05-12 杭州左蓝微电子技术有限公司 一种薄膜体声波谐振器锲形形状薄膜制备方法及器件

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5493129A (en) * 1988-06-29 1996-02-20 Hitachi, Ltd. Thin film transistor structure having increased on-current
US5270567A (en) 1989-09-06 1993-12-14 Casio Computer Co., Ltd. Thin film transistors without capacitances between electrodes thereof
JPH04505832A (ja) * 1990-10-05 1992-10-08 ゼネラル・エレクトリック・カンパニイ 改良されたソース/ドレイン接点を持つ薄膜トランジスタ構造
JPH04198923A (ja) * 1990-11-28 1992-07-20 Mitsubishi Electric Corp 表示装置の製造方法
JP2862737B2 (ja) * 1992-09-02 1999-03-03 シャープ株式会社 薄膜トランジスタ及びその製造方法
US5691782A (en) * 1994-07-08 1997-11-25 Sanyo Electric Co., Ltd. Liquid-crystal display with inter-line short-circuit preventive function and process for producing same
JP2776336B2 (ja) * 1995-09-26 1998-07-16 日本電気株式会社 薄膜トランジスタおよび薄膜トランジスタの製造方法
JP2865039B2 (ja) * 1995-12-26 1999-03-08 日本電気株式会社 薄膜トランジスタ基板の製造方法
CN1148600C (zh) * 1996-11-26 2004-05-05 三星电子株式会社 薄膜晶体管基片及其制造方法
JPH10209462A (ja) * 1997-01-27 1998-08-07 Advanced Display:Kk 薄膜トランジスタおよびその製法
JPH10282520A (ja) * 1997-04-03 1998-10-23 Hitachi Ltd 液晶表示装置
KR100262953B1 (ko) * 1997-06-11 2000-08-01 구본준 액정 표시 장치 및 그 액정 표시 장치의 제조 방법
JPH1117188A (ja) * 1997-06-23 1999-01-22 Sharp Corp アクティブマトリクス基板
US6369410B1 (en) * 1997-12-15 2002-04-09 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of manufacturing the semiconductor device
US6259119B1 (en) * 1997-12-18 2001-07-10 Lg. Philips Lcd Co, Ltd. Liquid crystal display and method of manufacturing the same
KR100301803B1 (ko) * 1998-06-05 2001-09-22 김영환 박막트랜지스터 및 그의 제조방법
JP2001094238A (ja) * 1999-07-16 2001-04-06 Sharp Corp 金属配線の製造方法およびその金属配線を備えた配線基板
GB9919913D0 (en) * 1999-08-24 1999-10-27 Koninkl Philips Electronics Nv Thin-film transistors and method for producing the same

Also Published As

Publication number Publication date
CN100429754C (zh) 2008-10-29
DE60124704D1 (de) 2007-01-04
US6768134B2 (en) 2004-07-27
US6693000B2 (en) 2004-02-17
CN1630938A (zh) 2005-06-22
JP4630420B2 (ja) 2011-02-09
WO2001091172A2 (en) 2001-11-29
JP2001332735A (ja) 2001-11-30
EP1290723A2 (de) 2003-03-12
EP1290723B1 (de) 2006-11-22
DE60124704T2 (de) 2007-03-15
US20040082123A1 (en) 2004-04-29
US20020048863A1 (en) 2002-04-25
WO2001091172A3 (en) 2002-03-21
KR100765305B1 (ko) 2007-10-10
KR20020032533A (ko) 2002-05-03

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