ATE350764T1 - Verfahren zur selbst-justierten herstellung von implantierten gebieten - Google Patents

Verfahren zur selbst-justierten herstellung von implantierten gebieten

Info

Publication number
ATE350764T1
ATE350764T1 AT99200531T AT99200531T ATE350764T1 AT E350764 T1 ATE350764 T1 AT E350764T1 AT 99200531 T AT99200531 T AT 99200531T AT 99200531 T AT99200531 T AT 99200531T AT E350764 T1 ATE350764 T1 AT E350764T1
Authority
AT
Austria
Prior art keywords
self
implanted areas
adjustable production
adjustable
production
Prior art date
Application number
AT99200531T
Other languages
English (en)
Inventor
Ricardo Alves Donaton
Karen Irma Josef Maex
Rita Verbeeck
Philippe Jansen
Rita Rooyackers
Ludo Deferm
Mikhail Rodionovich Baklanov
Original Assignee
Imec Inter Uni Micro Electr
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Imec Inter Uni Micro Electr filed Critical Imec Inter Uni Micro Electr
Application granted granted Critical
Publication of ATE350764T1 publication Critical patent/ATE350764T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0218—Manufacture or treatment of FETs having insulated gates [IGFET] having pocket halo regions selectively formed at the sides of the gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/022—Manufacture or treatment of FETs having insulated gates [IGFET] having lightly-doped source or drain extensions selectively formed at the sides of the gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/015—Manufacture or treatment removing at least parts of gate spacers, e.g. disposable spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F30/00—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors
    • H10F30/20—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors
    • H10F30/21—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation
    • H10F30/22—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation the devices having only one potential barrier, e.g. photodiodes
    • H10F30/227—Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation the devices having only one potential barrier, e.g. photodiodes the potential barrier being a Schottky barrier
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/222—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/351—Substrate regions of field-effect devices
    • H10D62/357—Substrate regions of field-effect devices of FETs
    • H10D62/364—Substrate regions of field-effect devices of FETs of IGFETs
    • H10D62/371—Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Light Receiving Elements (AREA)
  • Weting (AREA)
  • Drying Of Semiconductors (AREA)
  • Bipolar Transistors (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Organic Low-Molecular-Weight Compounds And Preparation Thereof (AREA)
AT99200531T 1995-06-19 1996-06-19 Verfahren zur selbst-justierten herstellung von implantierten gebieten ATE350764T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US242695P 1995-06-19 1995-06-19

Publications (1)

Publication Number Publication Date
ATE350764T1 true ATE350764T1 (de) 2007-01-15

Family

ID=21700706

Family Applications (2)

Application Number Title Priority Date Filing Date
AT99200531T ATE350764T1 (de) 1995-06-19 1996-06-19 Verfahren zur selbst-justierten herstellung von implantierten gebieten
AT96870078T ATE231286T1 (de) 1995-06-19 1996-06-19 Ätzverfahren für cosi2-schichten und verfahren zur herstellung von schottky-barrieren detektoren unter verwendung desselben

Family Applications After (1)

Application Number Title Priority Date Filing Date
AT96870078T ATE231286T1 (de) 1995-06-19 1996-06-19 Ätzverfahren für cosi2-schichten und verfahren zur herstellung von schottky-barrieren detektoren unter verwendung desselben

Country Status (4)

Country Link
US (2) US6153484A (de)
EP (1) EP0750338B1 (de)
AT (2) ATE350764T1 (de)
DE (2) DE69625747T2 (de)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3183249B2 (ja) * 1998-03-30 2001-07-09 日本電気株式会社 高抵抗負荷スタチック型ｒａｍの製造方法
US20030235936A1 (en) * 1999-12-16 2003-12-25 Snyder John P. Schottky barrier CMOS device and method
US7217977B2 (en) 2004-04-19 2007-05-15 Hrl Laboratories, Llc Covert transformation of transistor properties as a circuit protection method
US6692976B1 (en) * 2000-08-31 2004-02-17 Agilent Technologies, Inc. Post-etch cleaning treatment
US6368963B1 (en) * 2000-09-12 2002-04-09 Advanced Micro Devices, Inc. Passivation of semiconductor device surfaces using an iodine/ethanol solution
US6815816B1 (en) 2000-10-25 2004-11-09 Hrl Laboratories, Llc Implanted hidden interconnections in a semiconductor device for preventing reverse engineering
US6740942B2 (en) 2001-06-15 2004-05-25 Hrl Laboratories, Llc. Permanently on transistor implemented using a double polysilicon layer CMOS process with buried contact
KR20040072738A (ko) 2002-01-23 2004-08-18 스피나커 세미컨덕터, 인크. 변형 반도체 기판과 쇼트키 또는 쇼트키 콘택트와 유사한콘택트를 형성하는 소스 및/또는 드레인을 갖는 전계 효과트랜지스터
US6974737B2 (en) * 2002-05-16 2005-12-13 Spinnaker Semiconductor, Inc. Schottky barrier CMOS fabrication method
US7049667B2 (en) 2002-09-27 2006-05-23 Hrl Laboratories, Llc Conductive channel pseudo block process and circuit to inhibit reverse engineering
US6979606B2 (en) * 2002-11-22 2005-12-27 Hrl Laboratories, Llc Use of silicon block process step to camouflage a false transistor
GB2430800B (en) * 2002-11-22 2007-06-27 Hrl Lab Llc Use of silicon block process step to camouflage a false transistor
JP4846239B2 (ja) 2002-12-13 2011-12-28 エイチアールエル ラボラトリーズ，エルエルシー ウェル注入を用いた集積回路の改変
US6905923B1 (en) 2003-07-15 2005-06-14 Advanced Micro Devices, Inc. Offset spacer process for forming N-type transistors
US7179745B1 (en) * 2004-06-04 2007-02-20 Advanced Micro Devices, Inc. Method for offsetting a silicide process from a gate electrode of a semiconductor device
US7242063B1 (en) 2004-06-29 2007-07-10 Hrl Laboratories, Llc Symmetric non-intrusive and covert technique to render a transistor permanently non-operable
US7371333B2 (en) * 2005-06-07 2008-05-13 Micron Technology, Inc. Methods of etching nickel silicide and cobalt silicide and methods of forming conductive lines
US8168487B2 (en) 2006-09-28 2012-05-01 Hrl Laboratories, Llc Programmable connection and isolation of active regions in an integrated circuit using ambiguous features to confuse a reverse engineer
US8193602B2 (en) 2010-04-20 2012-06-05 Texas Instruments Incorporated Schottky diode with control gate for optimization of the on state resistance, the reverse leakage, and the reverse breakdown
CN104752168B (zh) * 2015-04-23 2017-10-17 上海华力微电子有限公司 一种去除鳍式场效应晶体管中掺磷碳化硅薄膜缺陷的方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4378628A (en) * 1981-08-27 1983-04-05 Bell Telephone Laboratories, Incorporated Cobalt silicide metallization for semiconductor integrated circuits
US4569722A (en) * 1984-11-23 1986-02-11 At&T Bell Laboratories Ethylene glycol etch for processes using metal silicides
GB2214349B (en) * 1988-01-19 1991-06-26 Standard Microsyst Smc Process for fabricating mos devices
US5821175A (en) * 1988-07-08 1998-10-13 Cauldron Limited Partnership Removal of surface contaminants by irradiation using various methods to achieve desired inert gas flow over treated surface
US4990988A (en) * 1989-06-09 1991-02-05 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Laterally stacked Schottky diodes for infrared sensor applications
US5290715A (en) * 1991-12-31 1994-03-01 U.S. Philips Corporation Method of making dielectrically isolated metal base transistors and permeable base transistors
US5605865A (en) * 1995-04-03 1997-02-25 Motorola Inc. Method for forming self-aligned silicide in a semiconductor device using vapor phase reaction
US5728625A (en) * 1996-04-04 1998-03-17 Lucent Technologies Inc. Process for device fabrication in which a thin layer of cobalt silicide is formed
US5780362A (en) * 1996-06-04 1998-07-14 Wang; Qingfeng CoSi2 salicide method
US5814537A (en) * 1996-12-18 1998-09-29 Sharp Microelectronics Technology,Inc. Method of forming transistor electrodes from directionally deposited silicide
US5849091A (en) * 1997-06-02 1998-12-15 Micron Technology, Inc. Megasonic cleaning methods and apparatus
US5934980A (en) * 1997-06-09 1999-08-10 Micron Technology, Inc. Method of chemical mechanical polishing
US5834356A (en) * 1997-06-27 1998-11-10 Vlsi Technology, Inc. Method of making high resistive structures in salicided process semiconductor devices
US6074960A (en) * 1997-08-20 2000-06-13 Micron Technology, Inc. Method and composition for selectively etching against cobalt silicide
US5937319A (en) * 1997-10-31 1999-08-10 Advanced Micro Devices, Inc. Method of making a metal oxide semiconductor (MOS) transistor polysilicon gate with a size beyond photolithography limitation by using polysilicidation and selective etching

Also Published As

Publication number Publication date
EP0750338A3 (de) 1997-04-16
ATE231286T1 (de) 2003-02-15
US6255227B1 (en) 2001-07-03
DE69625747T2 (de) 2003-10-23
EP0750338A2 (de) 1996-12-27
DE69636818D1 (de) 2007-02-15
US6153484A (en) 2000-11-28
DE69636818T2 (de) 2007-11-08
EP0750338B1 (de) 2003-01-15
DE69625747D1 (de) 2003-02-20

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