ATE352065T1 - Adaptiver cache-algorithmus für temperaturempfindlichen speicher - Google Patents

Adaptiver cache-algorithmus für temperaturempfindlichen speicher

Info

Publication number
ATE352065T1
ATE352065T1 AT04783776T AT04783776T ATE352065T1 AT E352065 T1 ATE352065 T1 AT E352065T1 AT 04783776 T AT04783776 T AT 04783776T AT 04783776 T AT04783776 T AT 04783776T AT E352065 T1 ATE352065 T1 AT E352065T1
Authority
AT
Austria
Prior art keywords
temperature sensitive
memory
sensitive memory
cache algorithm
adaptive cache
Prior art date
Application number
AT04783776T
Other languages
English (en)
Inventor
Richard Coulson
Brian Leete
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of ATE352065T1 publication Critical patent/ATE352065T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/20—Cooling means
    • G06F1/206—Cooling means comprising thermal management
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/20—Cooling means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Quality & Reliability (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Pens And Brushes (AREA)
AT04783776T 2003-09-11 2004-09-10 Adaptiver cache-algorithmus für temperaturempfindlichen speicher ATE352065T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/660,310 US7233880B2 (en) 2003-09-11 2003-09-11 Adaptive cache algorithm for temperature sensitive memory

Publications (1)

Publication Number Publication Date
ATE352065T1 true ATE352065T1 (de) 2007-02-15

Family

ID=34273636

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04783776T ATE352065T1 (de) 2003-09-11 2004-09-10 Adaptiver cache-algorithmus für temperaturempfindlichen speicher

Country Status (9)

Country Link
US (2) US7233880B2 (de)
EP (1) EP1668514B1 (de)
JP (1) JP3990439B2 (de)
KR (1) KR100824476B1 (de)
CN (1) CN100573475C (de)
AT (1) ATE352065T1 (de)
DE (1) DE602004004414T2 (de)
MY (1) MY138458A (de)
WO (1) WO2005026965A1 (de)

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JP5787840B2 (ja) 2012-07-26 2015-09-30 株式会社東芝 記憶システムおよび記憶システムのデータ書き込み方法
US9584617B2 (en) * 2013-12-31 2017-02-28 Successfactors, Inc. Allocating cache request in distributed cache system based upon cache object and marker identifying mission critical data
US9740426B2 (en) 2014-09-19 2017-08-22 Lenovo (Singapore) Pte. Ltd. Drive array policy control
TWI637268B (zh) * 2017-03-22 2018-10-01 慧榮科技股份有限公司 主機裝置與資料傳輸速率控制方法
US10013194B1 (en) * 2017-06-02 2018-07-03 Western Digital Technologies, Inc. Handling thermal shutdown for memory devices
US10572388B2 (en) 2017-08-30 2020-02-25 Micron Technology, Inc. Managed NVM adaptive cache management
KR20190064033A (ko) * 2017-11-30 2019-06-10 에스케이하이닉스 주식회사 메모리 컨트롤러, 이를 포함하는 메모리 시스템 및 이의 동작 방법
US10929062B2 (en) 2018-11-07 2021-02-23 International Business Machines Corporation Gradually throttling memory due to dynamic thermal conditions
KR102911989B1 (ko) 2019-11-28 2026-01-12 삼성전자 주식회사 메모리에 데이터를 기입하기 위한 장치 및 방법
CN113707192B (zh) * 2021-09-01 2023-02-28 合肥兆芯电子有限公司 存储器温控调频方法及存储器温控调频系统
CN117632011A (zh) * 2023-11-24 2024-03-01 中国联合网络通信集团有限公司 设备存储的控制方法、设备及存储介质

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Also Published As

Publication number Publication date
US7233880B2 (en) 2007-06-19
MY138458A (en) 2009-06-30
KR100824476B1 (ko) 2008-04-22
DE602004004414D1 (de) 2007-03-08
EP1668514B1 (de) 2007-01-17
EP1668514A1 (de) 2006-06-14
CN1849593A (zh) 2006-10-18
US20050060126A1 (en) 2005-03-17
US20060122805A1 (en) 2006-06-08
CN100573475C (zh) 2009-12-23
DE602004004414T2 (de) 2007-08-23
WO2005026965A1 (en) 2005-03-24
JP3990439B2 (ja) 2007-10-10
JP2007505406A (ja) 2007-03-08
KR20060063979A (ko) 2006-06-12

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