ATE352919T1 - Anordnung zur erfassung von daten - Google Patents

Anordnung zur erfassung von daten

Info

Publication number
ATE352919T1
ATE352919T1 AT01970444T AT01970444T ATE352919T1 AT E352919 T1 ATE352919 T1 AT E352919T1 AT 01970444 T AT01970444 T AT 01970444T AT 01970444 T AT01970444 T AT 01970444T AT E352919 T1 ATE352919 T1 AT E352919T1
Authority
AT
Austria
Prior art keywords
clock
phase
data
clock signal
data stream
Prior art date
Application number
AT01970444T
Other languages
English (en)
Inventor
Clifford D Fyvie
Original Assignee
Infineon Technologies Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Ag filed Critical Infineon Technologies Ag
Application granted granted Critical
Publication of ATE352919T1 publication Critical patent/ATE352919T1/de

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
    • H03L7/0996—Selecting a signal among the plurality of phase-shifted signals produced by the ring oscillator
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Apparatus For Radiation Diagnosis (AREA)
  • Burglar Alarm Systems (AREA)
  • Ultra Sonic Daignosis Equipment (AREA)
  • Indicating And Signalling Devices For Elevators (AREA)
  • Finger-Pressure Massage (AREA)
AT01970444T 2000-11-10 2001-09-24 Anordnung zur erfassung von daten ATE352919T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SE0004115A SE519113C2 (sv) 2000-11-10 2000-11-10 Anordning för fångning av data

Publications (1)

Publication Number Publication Date
ATE352919T1 true ATE352919T1 (de) 2007-02-15

Family

ID=20281771

Family Applications (1)

Application Number Title Priority Date Filing Date
AT01970444T ATE352919T1 (de) 2000-11-10 2001-09-24 Anordnung zur erfassung von daten

Country Status (8)

Country Link
US (1) US6973149B2 (de)
EP (1) EP1336270B1 (de)
AT (1) ATE352919T1 (de)
AU (1) AU2001290445A1 (de)
DE (1) DE60126316T2 (de)
SE (1) SE519113C2 (de)
TW (1) TWI234929B (de)
WO (1) WO2002039652A1 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003202936A (ja) * 2002-01-08 2003-07-18 Mitsubishi Electric Corp 半導体集積回路
JP4031671B2 (ja) * 2002-06-11 2008-01-09 松下電器産業株式会社 クロックリカバリ回路
US7246018B1 (en) * 2003-12-22 2007-07-17 Marvell International Ltd. Interpolator testing circuit
US7436921B1 (en) * 2004-11-05 2008-10-14 Rockwell Collins, Inc. Frequency sampling phase detector
US7599457B2 (en) * 2005-08-08 2009-10-06 Lattice Semiconductor Corporation Clock-and-data-recovery system having a multi-phase clock generator for one or more channel circuits
TWI316329B (en) * 2006-04-26 2009-10-21 Realtek Semiconductor Corp Phase selector, data receiving device, data transmitting device utilizing phase selector and clock-selecting method
KR101466850B1 (ko) * 2008-12-29 2014-12-11 주식회사 동부하이텍 데이터 전송 장치
CN104135413B (zh) * 2014-07-29 2017-06-13 北京航天自动控制研究所 一种适用于多点互联应用场合的高速串行总线采样系统

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5090024A (en) * 1989-08-23 1992-02-18 Intellon Corporation Spread spectrum communications system for networks
KR960002463B1 (ko) * 1993-12-11 1996-02-17 한국전기통신공사 고속데이타 전송에서의 디지틀 데이타 리타이밍 장치
JP2991023B2 (ja) * 1993-12-28 1999-12-20 株式会社日立製作所 データ送信装置、データ送受信装置及びシステム
US5557225A (en) * 1994-12-30 1996-09-17 Intel Corporation Pulsed flip-flop circuit
US6002685A (en) * 1996-12-04 1999-12-14 Alcatel Usa Sourcing, L.P. Time slot interchanger and digital communications terminal for ISDN D-channel assembly
US5905734A (en) * 1996-12-04 1999-05-18 Alcatel Usa Sourcing, L.P. Time slot interchanger and digital communications terminal for ISDN D-channel assembly
JP3072833B2 (ja) * 1997-05-23 2000-08-07 日本電気株式会社 ディジタルｐｌｌ回路
US6262611B1 (en) * 1999-06-24 2001-07-17 Nec Corporation High-speed data receiving circuit and method
US7289543B2 (en) * 2002-08-06 2007-10-30 Broadcom Corporation System and method for testing the operation of a DLL-based interface
JP4220320B2 (ja) * 2003-07-10 2009-02-04 株式会社日立製作所 半導体集積回路装置

Also Published As

Publication number Publication date
WO2002039652A1 (en) 2002-05-16
TWI234929B (en) 2005-06-21
US20020080899A1 (en) 2002-06-27
SE0004115D0 (sv) 2000-11-10
EP1336270A1 (de) 2003-08-20
EP1336270B1 (de) 2007-01-24
SE519113C2 (sv) 2003-01-14
US6973149B2 (en) 2005-12-06
DE60126316D1 (de) 2007-03-15
SE0004115L (sv) 2002-05-11
AU2001290445A1 (en) 2002-05-21
DE60126316T2 (de) 2007-11-15

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Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties