ATE357096T1 - Verfahren und schaltung zur verbesserung der pointerverwaltung in sdh-übertragungsrahmen - Google Patents

Verfahren und schaltung zur verbesserung der pointerverwaltung in sdh-übertragungsrahmen

Info

Publication number: ATE357096T1
Authority: AT; Austria
Prior art keywords: circuit; improving; stm; concatenation; case
Prior art date: 1998-11-03

Application number

AT99440292T

Other languages

English (en)

Inventor

Alessandra Rossi

Alberto Lometti

Giovanni Traverso

Claudio Girardi

Sergio Cabrini

Luca Razzetti

Alberto Bellato

Original Assignee

Cit Alcatel

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1998-11-03

Filing date

1999-10-29

Publication date

2007-04-15

1998-11-03 Priority claimed from IT002354 external-priority patent/IT1303297B1/it

1999-07-28 Priority claimed from IT99MI001674 external-priority patent/IT1313256B1/it

1999-10-29 Application filed by Cit Alcatel filed Critical Cit Alcatel

2007-04-15 Application granted granted Critical

2007-04-15 Publication of ATE357096T1 publication Critical patent/ATE357096T1/de

Links

238000000034 method Methods 0.000 title abstract 3
230000005540 biological transmission Effects 0.000 title abstract 2
VLCQZHSMCYCDJL-UHFFFAOYSA-N tribenuron methyl Chemical compound COC(=O)C1=CC=CC=C1S(=O)(=O)NC(=O)N(C)C1=NC(C)=NC(OC)=N1 VLCQZHSMCYCDJL-UHFFFAOYSA-N 0.000 title 1
238000010586 diagram Methods 0.000 abstract 2
230000001360 synchronised effect Effects 0.000 abstract 1

Classifications

- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
- H04J3/0623—Synchronous multiplexing systems, e.g. synchronous digital hierarchy/synchronous optical network (SDH/SONET), synchronisation with a pointer process

Landscapes

Engineering & Computer Science (AREA)
Computer Hardware Design (AREA)
Computer Networks & Wireless Communication (AREA)
Signal Processing (AREA)
Time-Division Multiplex Systems (AREA)
Mobile Radio Communication Systems (AREA)
Data Exchanges In Wide-Area Networks (AREA)

AT99440292T 1998-11-03 1999-10-29 Verfahren und schaltung zur verbesserung der pointerverwaltung in sdh-übertragungsrahmen ATE357096T1 (de)

Applications Claiming Priority (2)

Application Number	Priority Date	Filing Date	Title
IT002354 IT1303297B1 (it)	1998-11-03	1998-11-03	Metodo e circuito per migliorare l'elaborazione del puntatore in trameper trasmissioni e gerarchia numerica sincrona (sdh).
IT99MI001674 IT1313256B1 (it)	1999-07-28	1999-07-28	Metodo e circuito modulare per l'elaborazione del puntatore in tramesdh per trasmissioni.

Publications (1)

Publication Number	Publication Date
ATE357096T1 true ATE357096T1 (de)	2007-04-15

Family

ID=26331619

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
AT99440292T ATE357096T1 (de)	1998-11-03	1999-10-29	Verfahren und schaltung zur verbesserung der pointerverwaltung in sdh-übertragungsrahmen

Country Status (6)

Country	Link
US (1)	US6683890B1 (de)
EP (1)	EP0999667B1 (de)
JP (1)	JP2000151536A (de)
AT (1)	ATE357096T1 (de)
CA (1)	CA2287610A1 (de)
DE (1)	DE69935485T2 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US6973041B1 (en) *	2000-06-15	2005-12-06	Cisco Technology, Inc.	Path AIS insertion for concatenated payloads across multiple processors
EP1367751A1 (de) *	2002-05-28	2003-12-03	Alcatel	Rückfall bei Übertragung von Datensignalen über ein synchrones digitales Netz mit virtuellen verknüpften Containern
DE60322063D1 (de) *	2003-10-14	2008-08-21	Alcatel Lucent	Verbesserte Verwaltung von Pointerprozessoren bei verketteter Nutzlast in SDH oder SONET Rahmen
US8179785B1 (en) *	2010-02-17	2012-05-15	Tellabs Operations, Inc.	Deterministic switching protection over aggregated links

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
FI91698C (fi) *	1992-07-01	1994-07-25	Nokia Telecommunications Oy	Menetelmä synkronisessa digitaalisessa tietoliikennejärjestelmässä käytettävän signaalin vastaanottamiseksi
FI91697C (fi) *	1992-07-01	1994-07-25	Nokia Telecommunications Oy	Menetelmä synkronisessa digitaalisessa tietoliikennejärjestelmässä käytettävän signaalin vastaanottamiseksi
FI94813C (fi) *	1993-11-12	1995-10-25	Nokia Telecommunications Oy	Menetelmä synkronisessa digitaalisessa tietoliikennejärjestelmässä käytettävän signaalin vastaanottamiseksi
US6094440A (en) *	1996-07-05	2000-07-25	Hitachi, Ltd.	Multiplex type transmitting apparatus

1999
- 1999-10-26 CA CA002287610A patent/CA2287610A1/en not_active Abandoned
- 1999-10-27 JP JP11304895A patent/JP2000151536A/ja active Pending
- 1999-10-29 AT AT99440292T patent/ATE357096T1/de not_active IP Right Cessation
- 1999-10-29 EP EP99440292A patent/EP0999667B1/de not_active Expired - Lifetime
- 1999-10-29 DE DE69935485T patent/DE69935485T2/de not_active Expired - Lifetime
- 1999-11-02 US US09/432,279 patent/US6683890B1/en not_active Expired - Fee Related

Also Published As

Publication number	Publication date
EP0999667A3 (de)	2003-12-17
DE69935485D1 (de)	2007-04-26
EP0999667B1 (de)	2007-03-14
JP2000151536A (ja)	2000-05-30
CA2287610A1 (en)	2000-05-03
US6683890B1 (en)	2004-01-27
EP0999667A2 (de)	2000-05-10
DE69935485T2 (de)	2007-11-29

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Legal Events

Date	Code	Title	Description
2007-09-15	RER	Ceased as to paragraph 5 lit. 3 law introducing patent treaties