ATE358925T1 - Schnell verriegelnde takt- und datenrückgewinnungseinheit - Google Patents

Schnell verriegelnde takt- und datenrückgewinnungseinheit

Info

Publication number
ATE358925T1
ATE358925T1 AT04090018T AT04090018T ATE358925T1 AT E358925 T1 ATE358925 T1 AT E358925T1 AT 04090018 T AT04090018 T AT 04090018T AT 04090018 T AT04090018 T AT 04090018T AT E358925 T1 ATE358925 T1 AT E358925T1
Authority
AT
Austria
Prior art keywords
ring
clock
phase
data
recovery unit
Prior art date
Application number
AT04090018T
Other languages
English (en)
Inventor
Ashish K Choudhury
Timothy V Coe
Original Assignee
Vitesse Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Vitesse Semiconductor Corp filed Critical Vitesse Semiconductor Corp
Application granted granted Critical
Publication of ATE358925T1 publication Critical patent/ATE358925T1/de

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
    • H04L7/0338—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals the correction of the phase error being performed by a feed forward loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/046—Speed or phase control by synchronisation signals using special codes as synchronising signal using a dotting sequence

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Manipulation Of Pulses (AREA)
  • Communication Control (AREA)
AT04090018T 2004-01-19 2004-01-19 Schnell verriegelnde takt- und datenrückgewinnungseinheit ATE358925T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP04090018A EP1555776B1 (de) 2004-01-19 2004-01-19 Schnell verriegelnde Takt- und Datenrückgewinnungseinheit

Publications (1)

Publication Number Publication Date
ATE358925T1 true ATE358925T1 (de) 2007-04-15

Family

ID=34610211

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04090018T ATE358925T1 (de) 2004-01-19 2004-01-19 Schnell verriegelnde takt- und datenrückgewinnungseinheit

Country Status (3)

Country Link
EP (1) EP1555776B1 (de)
AT (1) ATE358925T1 (de)
DE (1) DE602004005658T2 (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102904706B (zh) * 2012-09-26 2015-02-25 烽火通信科技股份有限公司 分组传送网络中的系统频率同步装置及方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4672639A (en) * 1984-05-24 1987-06-09 Kabushiki Kaisha Toshiba Sampling clock pulse generator
JP2000031951A (ja) * 1998-07-15 2000-01-28 Fujitsu Ltd バースト同期回路
GB2385728B (en) * 2002-02-26 2006-07-12 Fujitsu Ltd Clock recovery circuitry

Also Published As

Publication number Publication date
EP1555776B1 (de) 2007-04-04
DE602004005658T2 (de) 2007-12-13
DE602004005658D1 (de) 2007-05-16
EP1555776A1 (de) 2005-07-20

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