ATE359554T1 - System mit adressbasierter intraknotenkohärenz und datenbasierter interknotenkohärenz - Google Patents

System mit adressbasierter intraknotenkohärenz und datenbasierter interknotenkohärenz

Info

Publication number
ATE359554T1
ATE359554T1 AT02025691T AT02025691T ATE359554T1 AT E359554 T1 ATE359554 T1 AT E359554T1 AT 02025691 T AT02025691 T AT 02025691T AT 02025691 T AT02025691 T AT 02025691T AT E359554 T1 ATE359554 T1 AT E359554T1
Authority
AT
Austria
Prior art keywords
interconnect
coherence
node
address
nodes
Prior art date
Application number
AT02025691T
Other languages
English (en)
Inventor
Joseph B Rowlands
Original Assignee
Broadcom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Broadcom Corp filed Critical Broadcom Corp
Application granted granted Critical
Publication of ATE359554T1 publication Critical patent/ATE359554T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S707/00—Data processing: database and file management or data structures
    • Y10S707/99951—File or database maintenance
    • Y10S707/99952—Coherency, e.g. same view to multiple users

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Image Processing (AREA)
  • Image Analysis (AREA)
AT02025691T 2002-05-15 2002-11-20 System mit adressbasierter intraknotenkohärenz und datenbasierter interknotenkohärenz ATE359554T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US38074002P 2002-05-15 2002-05-15
US10/270,480 US7003631B2 (en) 2002-05-15 2002-10-11 System having address-based intranode coherency and data-based internode coherency

Publications (1)

Publication Number Publication Date
ATE359554T1 true ATE359554T1 (de) 2007-05-15

Family

ID=29272889

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02025691T ATE359554T1 (de) 2002-05-15 2002-11-20 System mit adressbasierter intraknotenkohärenz und datenbasierter interknotenkohärenz

Country Status (4)

Country Link
US (1) US7003631B2 (de)
EP (1) EP1363191B1 (de)
AT (1) ATE359554T1 (de)
DE (1) DE60219436T2 (de)

Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7752281B2 (en) * 2001-11-20 2010-07-06 Broadcom Corporation Bridges performing remote reads and writes as uncacheable coherent operations
US6748479B2 (en) 2001-11-20 2004-06-08 Broadcom Corporation System having interfaces and switch that separates coherent and packet traffic
US7302505B2 (en) * 2001-12-24 2007-11-27 Broadcom Corporation Receiver multi-protocol interface and applications thereof
US6965973B2 (en) 2002-05-15 2005-11-15 Broadcom Corporation Remote line directory which covers subset of shareable CC-NUMA memory space
US7003631B2 (en) 2002-05-15 2006-02-21 Broadcom Corporation System having address-based intranode coherency and data-based internode coherency
US20050013294A1 (en) * 2003-04-11 2005-01-20 Sun Microsystems, Inc. Multi-node computer system with active devices employing promise arrays for outstanding transactions
GB2416416B (en) * 2003-04-11 2006-11-22 Sun Microsystems Inc Multi-node computer system implementing global access state dependent transactions
US7558920B2 (en) * 2004-06-30 2009-07-07 Intel Corporation Apparatus and method for partitioning a shared cache of a chip multi-processor
US7840755B2 (en) * 2005-05-24 2010-11-23 Lsi Corporation Methods and systems for automatically identifying a modification to a storage array
US7797495B1 (en) * 2005-08-04 2010-09-14 Advanced Micro Devices, Inc. Distributed directory cache
US7398360B2 (en) * 2005-08-17 2008-07-08 Sun Microsystems, Inc. Multi-socket symmetric multiprocessing (SMP) system for chip multi-threaded (CMT) processors
US7353340B2 (en) * 2005-08-17 2008-04-01 Sun Microsystems, Inc. Multiple independent coherence planes for maintaining coherency
US7529894B2 (en) * 2005-08-17 2009-05-05 Sun Microsystems, Inc. Use of FBDIMM channel as memory channel and coherence channel
US20070073832A1 (en) * 2005-09-27 2007-03-29 Curtis Bryce A Method and system of storing and accessing meta-data in a network adapter
US8458176B2 (en) * 2005-11-09 2013-06-04 Ca, Inc. Method and system for providing a directory overlay
US20070112791A1 (en) * 2005-11-09 2007-05-17 Harvey Richard H Method and system for providing enhanced read performance for a supplemental directory
US8321486B2 (en) * 2005-11-09 2012-11-27 Ca, Inc. Method and system for configuring a supplemental directory
US8326899B2 (en) * 2005-11-09 2012-12-04 Ca, Inc. Method and system for improving write performance in a supplemental directory
US7840618B2 (en) * 2006-01-03 2010-11-23 Nec Laboratories America, Inc. Wide area networked file system
US7702743B1 (en) * 2006-01-26 2010-04-20 Symantec Operating Corporation Supporting a weak ordering memory model for a virtual physical address space that spans multiple nodes
US7596654B1 (en) 2006-01-26 2009-09-29 Symantec Operating Corporation Virtual machine spanning multiple computers
US7756943B1 (en) 2006-01-26 2010-07-13 Symantec Operating Corporation Efficient data transfer between computers in a virtual NUMA system using RDMA
US20070179981A1 (en) * 2006-01-31 2007-08-02 International Business Machines Corporation Efficient data management in a cluster file system
US8019920B2 (en) * 2008-10-01 2011-09-13 Hewlett-Packard Development Company, L.P. Method to improve operating performance of a computing device
US9785462B2 (en) 2008-12-30 2017-10-10 Intel Corporation Registering a user-handler in hardware for transactional memory event handling
US8627017B2 (en) * 2008-12-30 2014-01-07 Intel Corporation Read and write monitoring attributes in transactional memory (TM) systems
US8984246B2 (en) * 2011-04-04 2015-03-17 Texas Instruments Incorporated Method, system and computer program product for reading a decision tree
JP5541275B2 (ja) * 2011-12-28 2014-07-09 富士通株式会社 情報処理装置および不正アクセス防止方法
US8972663B2 (en) * 2013-03-14 2015-03-03 Oracle International Corporation Broadcast cache coherence on partially-ordered network
US11240334B2 (en) * 2015-10-01 2022-02-01 TidalScale, Inc. Network attached memory using selective resource migration
CN107992436B (zh) * 2016-10-26 2021-04-09 华为技术有限公司 一种NVMe数据读写方法及NVMe设备
US11023135B2 (en) 2017-06-27 2021-06-01 TidalScale, Inc. Handling frequently accessed pages
US10817347B2 (en) 2017-08-31 2020-10-27 TidalScale, Inc. Entanglement of pages and guest threads
US11175927B2 (en) 2017-11-14 2021-11-16 TidalScale, Inc. Fast boot
US11119926B2 (en) 2017-12-18 2021-09-14 Advanced Micro Devices, Inc. Region based directory scheme to adapt to large cache sizes
US10705959B2 (en) 2018-08-31 2020-07-07 Advanced Micro Devices, Inc. Region based split-directory scheme to adapt to large cache sizes
US10922237B2 (en) 2018-09-12 2021-02-16 Advanced Micro Devices, Inc. Accelerating accesses to private regions in a region-based cache directory scheme
US11409286B2 (en) * 2019-12-18 2022-08-09 Intel Corporation Hardware random forest: low latency, fully reconfigurable ensemble classification
US11144978B1 (en) * 2021-02-25 2021-10-12 Mythical, Inc. Systems and methods to support custom bundling of virtual items within an online game

Family Cites Families (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CH670715A5 (de) 1986-10-03 1989-06-30 Bbc Brown Boveri & Cie
US5963745A (en) 1990-11-13 1999-10-05 International Business Machines Corporation APAP I/O programmable router
US5765011A (en) 1990-11-13 1998-06-09 International Business Machines Corporation Parallel processing system having a synchronous SIMD processing with processing elements emulating SIMD operation using individual instruction streams
US5634004A (en) 1994-05-16 1997-05-27 Network Programs, Inc. Directly programmable distribution element
EP0735487B1 (de) 1995-03-31 2001-10-31 Sun Microsystems, Inc. Schnelle Zweitor-Cachesteuerungsschaltung für Datenprozessoren in einem paketvermittelten cachekohärenten Multiprozessorsystem
US5644756A (en) * 1995-04-07 1997-07-01 Motorola, Inc. Integrated circuit data processor with selectable routing of data accesses
US5805920A (en) 1995-11-13 1998-09-08 Tandem Computers Incorporated Direct bulk data transfers
US5710907A (en) 1995-12-22 1998-01-20 Sun Microsystems, Inc. Hybrid NUMA COMA caching system and methods for selecting between the caching modes
US5887138A (en) 1996-07-01 1999-03-23 Sun Microsystems, Inc. Multiprocessing computer system employing local and global address spaces and COMA and NUMA access modes
US5878268A (en) 1996-07-01 1999-03-02 Sun Microsystems, Inc. Multiprocessing system configured to store coherency state within multiple subnodes of a processing node
US5813029A (en) 1996-07-09 1998-09-22 Micron Electronics, Inc. Upgradeable cache circuit using high speed multiplexer
US5961623A (en) 1996-08-29 1999-10-05 Apple Computer, Inc. Method and system for avoiding starvation and deadlocks in a split-response interconnect of a computer system
JPH10154100A (ja) 1996-11-25 1998-06-09 Canon Inc 情報処理システム及び装置及びその制御方法
JP3904282B2 (ja) 1997-03-31 2007-04-11 株式会社ルネサステクノロジ 半導体集積回路装置
US6105119A (en) 1997-04-04 2000-08-15 Texas Instruments Incorporated Data transfer circuitry, DSP wrapper circuitry and improved processor devices, methods and systems
US6298370B1 (en) 1997-04-04 2001-10-02 Texas Instruments Incorporated Computer operating process allocating tasks between first and second processors at run time based upon current processor load
US6182201B1 (en) 1997-04-14 2001-01-30 International Business Machines Corporation Demand-based issuance of cache operations to a system bus
FR2762418B1 (fr) 1997-04-17 1999-06-11 Alsthom Cge Alcatel Procede de gestion d'une memoire partagee
JP3524337B2 (ja) 1997-07-25 2004-05-10 キヤノン株式会社 バス管理装置及びそれを有する複合機器の制御装置
US6085295A (en) * 1997-10-20 2000-07-04 International Business Machines Corporation Method of maintaining data coherency in a computer system having a plurality of interconnected nodes
US6085294A (en) 1997-10-24 2000-07-04 Compaq Computer Corporation Distributed data dependency stall mechanism
US6209065B1 (en) 1997-10-24 2001-03-27 Compaq Computer Corporation Mechanism for optimizing generation of commit-signals in a distributed shared-memory system
US6108752A (en) 1997-10-24 2000-08-22 Compaq Computer Corporation Method and apparatus for delaying victim writes in a switch-based multi-processor system to maintain data coherency
US6101420A (en) 1997-10-24 2000-08-08 Compaq Computer Corporation Method and apparatus for disambiguating change-to-dirty commands in a switch based multi-processing system with coarse directories
US6032228A (en) 1997-11-26 2000-02-29 International Business Machines Corporation Flexible cache-coherency mechanism
US6141733A (en) 1998-02-17 2000-10-31 International Business Machines Corporation Cache coherency protocol with independent implementation of optimized cache operations
US6070215A (en) 1998-03-13 2000-05-30 Compaq Computer Corporation Computer system with improved transition to low power operation
GB9806184D0 (en) 1998-03-23 1998-05-20 Sgs Thomson Microelectronics A cache coherency mechanism
US6195739B1 (en) 1998-06-29 2001-02-27 Cisco Technology, Inc. Method and apparatus for passing data among processor complex stages of a pipelined processing engine
US6266731B1 (en) 1998-09-03 2001-07-24 Compaq Computer Corporation High speed peripheral interconnect apparatus, method and system
US6546429B1 (en) * 1998-09-21 2003-04-08 International Business Machines Corporation Non-uniform memory access (NUMA) data processing system that holds and reissues requests at a target processing node in response to a retry
US6338122B1 (en) * 1998-12-15 2002-01-08 International Business Machines Corporation Non-uniform memory access (NUMA) data processing system that speculatively forwards a read request to a remote processing node
US6108764A (en) * 1998-12-17 2000-08-22 International Business Machines Corporation Non-uniform memory access (NUMA) data processing system with multiple caches concurrently holding data in a recent state from which data can be sourced by shared intervention
US6631401B1 (en) 1998-12-21 2003-10-07 Advanced Micro Devices, Inc. Flexible probe/probe response routing for maintaining coherency
US6425060B1 (en) 1999-01-05 2002-07-23 International Business Machines Corporation Circuit arrangement and method with state-based transaction scheduling
US6266743B1 (en) * 1999-02-26 2001-07-24 International Business Machines Corporation Method and system for providing an eviction protocol within a non-uniform memory access system
US6279085B1 (en) * 1999-02-26 2001-08-21 International Business Machines Corporation Method and system for avoiding livelocks due to colliding writebacks within a non-uniform memory access system
US6766360B1 (en) * 2000-07-14 2004-07-20 Fujitsu Limited Caching mechanism for remote read-only data in a cache coherent non-uniform memory access (CCNUMA) architecture
US6725343B2 (en) * 2000-10-05 2004-04-20 Hewlett-Packard Development Company, L.P. System and method for generating cache coherence directory entries and error correction codes in a multiprocessor system
US7003631B2 (en) 2002-05-15 2006-02-21 Broadcom Corporation System having address-based intranode coherency and data-based internode coherency

Also Published As

Publication number Publication date
DE60219436D1 (de) 2007-05-24
DE60219436T2 (de) 2007-12-13
EP1363191B1 (de) 2007-04-11
US7003631B2 (en) 2006-02-21
EP1363191A1 (de) 2003-11-19
US20030217234A1 (en) 2003-11-20

Similar Documents

Publication Publication Date Title
ATE359554T1 (de) System mit adressbasierter intraknotenkohärenz und datenbasierter interknotenkohärenz
TWI311707B (en) Computer system with integrated directory and processor cache
US8255636B2 (en) Two-hop source snoop based messaging protocol
US6615319B2 (en) Distributed mechanism for resolving cache coherence conflicts in a multi-node computer architecture
US10019366B2 (en) Satisfying memory ordering requirements between partial reads and non-snoop accesses
EP1255201B1 (de) Multiprozessorsystem mit gemeinsamem Speicher, welches gemischte Broadcast-Snoop und verzeichnisbasierte Kohärenzprotokolle benutzt
JP5153172B2 (ja) アクセラレータ用低コストのキャッシュ一貫性を維持する方法及びシステム
ATE309574T1 (de) System mit schnittstellen, einem schalter und einer speicherbrücke mit cc-numa (cache-coherent non-uniform memory access)
JP2009064471A (ja) マルチプロセッサ・システムにおけるキャッシュ・コヒーレンスにおいて用いるフォワード状態
US20110004729A1 (en) Block Caching for Cache-Coherent Distributed Shared Memory
US20100005245A1 (en) Satisfying memory ordering requirements between partial writes and non-snoop accesses
US7818509B2 (en) Combined response cancellation for load command
US8693476B2 (en) Dynamic update of route table
JP2006516058A (ja) キャッシュ・コヒーレンス・プロトコルに対する投機的分散競合解決
CN101093464B (zh) 高速缓存一致性方法和对称多处理系统
US20050262250A1 (en) Messaging protocol
EP0981092A3 (de) Datenverarbeitungssystem mit nichtuniformen Speicherzugriffen (NUMA) welches die Latenzzeit verkürzt durch Versenden von ReRun-Anfragen
KR100257993B1 (ko) 분산 공유 메모리 시스템에서 미세 통신과 대단위 통신의 병합을 위한 적응형 입도 방법
US7568073B2 (en) Mechanisms and methods of cache coherence in network-based multiprocessor systems with ring-based snoop response collection
US7543115B1 (en) Two-hop source snoop based cache coherence protocol
WO2004092968A3 (en) Multi-node system with global access states
WO2001016737A2 (en) Cache-coherent shared-memory cluster
US20080005486A1 (en) Coordination of snoop responses in a multi-processor system
US20090006712A1 (en) Data ordering in a multi-node system
US20020129206A1 (en) Mechanism for handling conflicts in a multi-node computer architecture

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties