ATE364227T1 - Verfahren und system zur optimierung der testkosten und deaktivierungsdefekte für scan- und bist-speicher - Google Patents

Verfahren und system zur optimierung der testkosten und deaktivierungsdefekte für scan- und bist-speicher

Info

Publication number
ATE364227T1
ATE364227T1 AT02726654T AT02726654T ATE364227T1 AT E364227 T1 ATE364227 T1 AT E364227T1 AT 02726654 T AT02726654 T AT 02726654T AT 02726654 T AT02726654 T AT 02726654T AT E364227 T1 ATE364227 T1 AT E364227T1
Authority
AT
Austria
Prior art keywords
memory
scan
bist
integrated circuit
deactivation
Prior art date
Application number
AT02726654T
Other languages
English (en)
Inventor
Laung-Terng Wang
Shyh-Horng Lin
Hsin-Po Wang
Xiaoqing Wen
Chi-Chan Hsu
Anthony Vu
Yo Han Park
Original Assignee
Syntest Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Syntest Technologies Inc filed Critical Syntest Technologies Inc
Application granted granted Critical
Publication of ATE364227T1 publication Critical patent/ATE364227T1/de

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/30—Accessing single arrays
    • G11C29/32—Serial access; Scan testing
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318544—Scanning methods, algorithms and patterns
    • G01R31/318547—Data generators or compressors
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318558—Addressing or selecting of subparts of the device under test
    • G01R31/318563—Multiple simultaneous testing of subparts
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14—Implementation of control logic, e.g. test mode decoders
    • G11C29/16—Implementation of control logic, e.g. test mode decoders using microprogrammed units, e.g. state machines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/30—Accessing single arrays
    • G11C2029/3202—Scan chain

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Tests Of Electronic Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
AT02726654T 2001-04-10 2002-04-09 Verfahren und system zur optimierung der testkosten und deaktivierungsdefekte für scan- und bist-speicher ATE364227T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US28291701P 2001-04-10 2001-04-10
US10/116,128 US20020194558A1 (en) 2001-04-10 2002-04-05 Method and system to optimize test cost and disable defects for scan and BIST memories

Publications (1)

Publication Number Publication Date
ATE364227T1 true ATE364227T1 (de) 2007-06-15

Family

ID=26813916

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02726654T ATE364227T1 (de) 2001-04-10 2002-04-09 Verfahren und system zur optimierung der testkosten und deaktivierungsdefekte für scan- und bist-speicher

Country Status (5)

Country Link
US (1) US20020194558A1 (de)
EP (1) EP1377981B1 (de)
AT (1) ATE364227T1 (de)
DE (1) DE60220511T2 (de)
WO (1) WO2002084668A1 (de)

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Also Published As

Publication number Publication date
WO2002084668A1 (en) 2002-10-24
EP1377981A1 (de) 2004-01-07
DE60220511T2 (de) 2008-02-14
US20020194558A1 (en) 2002-12-19
EP1377981A4 (de) 2006-03-22
EP1377981B1 (de) 2007-06-06
DE60220511D1 (de) 2007-07-19

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