ATE364231T1 - Test für schwache sram-zellen - Google Patents

Test für schwache sram-zellen

Info

Publication number
ATE364231T1
ATE364231T1 AT04716681T AT04716681T ATE364231T1 AT E364231 T1 ATE364231 T1 AT E364231T1 AT 04716681 T AT04716681 T AT 04716681T AT 04716681 T AT04716681 T AT 04716681T AT E364231 T1 ATE364231 T1 AT E364231T1
Authority
AT
Austria
Prior art keywords
ratio
array
cells
bit lines
weak
Prior art date
Application number
AT04716681T
Other languages
English (en)
Inventor
De Gyvez Jose Pineda
Manoj Sachdev
Andrei Pavlov
Original Assignee
Koninkl Philips Electronics Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv filed Critical Koninkl Philips Electronics Nv
Application granted granted Critical
Publication of ATE364231T1 publication Critical patent/ATE364231T1/de

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C2029/5006—Current

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
AT04716681T 2003-03-12 2004-03-03 Test für schwache sram-zellen ATE364231T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP03100633 2003-03-12

Publications (1)

Publication Number Publication Date
ATE364231T1 true ATE364231T1 (de) 2007-06-15

Family

ID=32981919

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04716681T ATE364231T1 (de) 2003-03-12 2004-03-03 Test für schwache sram-zellen

Country Status (9)

Country Link
US (1) US7200057B2 (de)
EP (1) EP1606824B1 (de)
JP (1) JP2006520511A (de)
KR (1) KR101061080B1 (de)
CN (1) CN100437834C (de)
AT (1) ATE364231T1 (de)
DE (1) DE602004006848T2 (de)
TW (1) TW200428392A (de)
WO (1) WO2004081948A1 (de)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100437834C (zh) * 2003-03-12 2008-11-26 Nxp股份有限公司 用于弱sram单元的检测装置和方法
US7298659B1 (en) * 2004-06-07 2007-11-20 Virage Logic Corporation Method and system for accelerated detection of weak bits in an SRAM memory device
GB0426005D0 (en) * 2004-11-26 2004-12-29 Koninkl Philips Electronics Nv Sram test method and sram test arrangement
US20070025167A1 (en) * 2005-07-27 2007-02-01 Marco Ziegelmayer Method for testing a memory device, test unit for testing a memory device and memory device
EP2011123B1 (de) 2006-04-13 2015-03-04 Nxp B.V. Verfahren zur erzeugung eines halbleiterbauelementidentifikators und halbleiterbauelement
US7613067B2 (en) * 2006-10-20 2009-11-03 Manoj Sachdev Soft error robust static random access memory cells
US7606092B2 (en) 2007-02-01 2009-10-20 Analog Devices, Inc. Testing for SRAM memory data retention
JP4411443B2 (ja) * 2007-03-31 2010-02-10 国立大学法人九州工業大学 Ｓｒａｍメモリセルの評価方法及びｓｒａｍメモリセルの評価プログラム
US7480192B1 (en) * 2007-04-06 2009-01-20 Xilinx, Inc. Pull-up voltage circuit
US7646203B2 (en) * 2007-07-16 2010-01-12 United Microelectronics Corp. Defect detection system with multilevel output capability and method thereof
DE102008007029B4 (de) * 2008-01-31 2014-07-03 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Betrieb einer elektronischen Schaltung mit körpergesteuertem Doppelkanaltransistor und SRAM-Zelle mit körpergesteuertem Doppelkanaltransistor
US7715260B1 (en) 2008-12-01 2010-05-11 United Microelectronics Corp. Operating voltage tuning method for static random access memory
TWI423362B (zh) * 2008-12-09 2014-01-11 United Microelectronics Corp 靜態隨機存取記憶體的操作電壓的調整方法
US9842631B2 (en) * 2012-12-14 2017-12-12 Nvidia Corporation Mitigating external influences on long signal lines
US8976574B2 (en) 2013-03-13 2015-03-10 Qualcomm Incorporated Process corner sensor for bit-cells
US9959912B2 (en) 2016-02-02 2018-05-01 Qualcomm Incorporated Timed sense amplifier circuits and methods in a semiconductor memory
KR102471601B1 (ko) * 2016-05-17 2022-11-29 에스케이하이닉스 주식회사 반도체 메모리 장치 및 그의 위크 셀 검출 방법
KR102517700B1 (ko) * 2016-06-10 2023-04-05 에스케이하이닉스 주식회사 반도체 메모리 장치 및 그의 동작 방법
US10950296B2 (en) * 2018-07-16 2021-03-16 Taiwan Semiconductor Manufacturing Company, Ltd. Latch circuit formed from bit cell
CN111986719B (zh) * 2020-09-10 2022-11-29 苏州兆芯半导体科技有限公司 电流确定方法
US12087387B2 (en) 2022-03-02 2024-09-10 Samsung Electronics Co., Ltd. Methods and systems for managing read operation of memory device with single ended read path
US12045509B2 (en) * 2022-06-17 2024-07-23 SanDisk Technologies, Inc. Data storage device with weak bits handling
CN115641903B (zh) * 2022-10-19 2024-08-09 深圳市紫光同创电子有限公司 Fpga存储单元失效分析方法、装置、电子设备以及存储介质
CN115938456B (zh) * 2023-03-09 2023-07-25 长鑫存储技术有限公司 半导体存储装置的测试方法、装置、设备及介质

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0756759B2 (ja) * 1990-12-27 1995-06-14 株式会社東芝 スタティック型半導体記憶装置
US5559745A (en) * 1995-09-15 1996-09-24 Intel Corporation Static random access memory SRAM having weak write test circuit
US6501692B1 (en) * 2001-09-17 2002-12-31 Cirrus Logic, Inc. Circuit and method for stress testing a static random access memory (SRAM) device
CN100437834C (zh) * 2003-03-12 2008-11-26 Nxp股份有限公司 用于弱sram单元的检测装置和方法
KR100518579B1 (ko) * 2003-06-05 2005-10-04 삼성전자주식회사 반도체 장치 및 그 테스트 방법
US7133319B2 (en) * 2003-06-20 2006-11-07 Hewlett-Packard Development Company, L.P. Programmable weak write test mode (PWWTM) bias generation having logic high output default mode

Also Published As

Publication number Publication date
WO2004081948A1 (en) 2004-09-23
JP2006520511A (ja) 2006-09-07
US20060187724A1 (en) 2006-08-24
KR20050107786A (ko) 2005-11-15
CN100437834C (zh) 2008-11-26
US7200057B2 (en) 2007-04-03
TW200428392A (en) 2004-12-16
DE602004006848D1 (de) 2007-07-19
KR101061080B1 (ko) 2011-09-01
CN1759452A (zh) 2006-04-12
EP1606824A1 (de) 2005-12-21
DE602004006848T2 (de) 2008-02-07
EP1606824B1 (de) 2007-06-06

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