ATE370424T1 - Automatisches detektieren und routen von testsignalen - Google Patents

Automatisches detektieren und routen von testsignalen

Info

Publication number
ATE370424T1
ATE370424T1 AT04715833T AT04715833T ATE370424T1 AT E370424 T1 ATE370424 T1 AT E370424T1 AT 04715833 T AT04715833 T AT 04715833T AT 04715833 T AT04715833 T AT 04715833T AT E370424 T1 ATE370424 T1 AT E370424T1
Authority
AT
Austria
Prior art keywords
test signals
routing
test
circuit paths
automatic detection
Prior art date
Application number
AT04715833T
Other languages
English (en)
Inventor
Daniel Avery
Joel Bailey
Original Assignee
Koninkl Philips Electronics Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv filed Critical Koninkl Philips Electronics Nv
Application granted granted Critical
Publication of ATE370424T1 publication Critical patent/ATE370424T1/de

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318558—Addressing or selecting of subparts of the device under test
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/50—Testing arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Selective Calling Equipment (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
AT04715833T 2003-03-04 2004-02-28 Automatisches detektieren und routen von testsignalen ATE370424T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US45209503P 2003-03-04 2003-03-04

Publications (1)

Publication Number Publication Date
ATE370424T1 true ATE370424T1 (de) 2007-09-15

Family

ID=32962688

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04715833T ATE370424T1 (de) 2003-03-04 2004-02-28 Automatisches detektieren und routen von testsignalen

Country Status (7)

Country Link
US (1) US20060200715A1 (de)
EP (1) EP1601984B1 (de)
JP (1) JP2006519388A (de)
CN (1) CN1756962A (de)
AT (1) ATE370424T1 (de)
DE (1) DE602004008234T2 (de)
WO (1) WO2004079382A1 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6839242B2 (en) * 2003-02-13 2005-01-04 Rincon Research Corporation Reconfigurable circuit modules
US20050149783A1 (en) * 2003-12-11 2005-07-07 International Business Machines Corporation Methods and apparatus for testing an IC
US7464314B2 (en) * 2005-05-12 2008-12-09 Realtek Semiconductor Corp. Method for validating an integrated circuit and related semiconductor product thereof
FR2879297A1 (fr) * 2005-05-31 2006-06-16 France Telecom Systeme electronique comprenant une premiere et une deuxieme cartes electroniques chacune d'un bus de communication
JP5067266B2 (ja) 2008-06-04 2012-11-07 富士通株式会社 Ｊｔａｇ機能付き集積回路ボード
CN101871995B (zh) * 2009-04-23 2013-01-02 华为技术有限公司 一种jtag连接控制装置及单板
CN102353867A (zh) * 2011-06-08 2012-02-15 伟创力电子技术(苏州)有限公司 一种互连测试设备及其测试方法
CN110174531B (zh) * 2019-05-24 2021-08-03 成都飞机工业（集团）有限责任公司 飞机/悬挂物测试系统信号路径可重构接口电路

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5636227A (en) * 1994-07-08 1997-06-03 Advanced Risc Machines Limited Integrated circuit test mechansim and method
US6408413B1 (en) * 1998-02-18 2002-06-18 Texas Instruments Incorporated Hierarchical access of test access ports in embedded core integrated circuits
JP2001201543A (ja) * 2000-01-18 2001-07-27 Rooran:Kk スキャン・パス構築用プログラムを記録した記録媒体とスキャン・パスの構築方法及びこのスキャン・パスを組み込んだ演算処理システム
JP3980827B2 (ja) * 2000-03-10 2007-09-26 株式会社ルネサステクノロジ 半導体集積回路装置および製造方法
US6785854B1 (en) * 2000-10-02 2004-08-31 Koninklijke Philips Electronics N.V. Test access port (TAP) controller system and method to debug internal intermediate scan test faults
EP1286279A1 (de) * 2001-08-21 2003-02-26 Alcatel Konfigurations tool
US7047457B1 (en) * 2003-09-11 2006-05-16 Xilinx, Inc. Testing of a multi-gigabit transceiver

Also Published As

Publication number Publication date
DE602004008234T2 (de) 2008-05-08
WO2004079382A1 (en) 2004-09-16
JP2006519388A (ja) 2006-08-24
CN1756962A (zh) 2006-04-05
DE602004008234D1 (de) 2007-09-27
US20060200715A1 (en) 2006-09-07
EP1601984A1 (de) 2005-12-07
EP1601984B1 (de) 2007-08-15

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Legal Events

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