ATE376303T1 - Verfahren und brückenelement-modul - Google Patents

Verfahren und brückenelement-modul

Info

Publication number
ATE376303T1
ATE376303T1 AT03011314T AT03011314T ATE376303T1 AT E376303 T1 ATE376303 T1 AT E376303T1 AT 03011314 T AT03011314 T AT 03011314T AT 03011314 T AT03011314 T AT 03011314T AT E376303 T1 ATE376303 T1 AT E376303T1
Authority
AT
Austria
Prior art keywords
bridge element
protocol
element module
enabled module
bridge
Prior art date
Application number
AT03011314T
Other languages
English (en)
Inventor
Jeffrey M Harris
Malcolm Rush
Robert Tufford
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Application granted granted Critical
Publication of ATE376303T1 publication Critical patent/ATE376303T1/de

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/46—Interconnection of networks
    • H04L12/4604—LAN interconnection over a backbone network, e.g. Internet, Frame Relay
    • H04L12/462—LAN interconnection over a bridge based backbone
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Signal Processing (AREA)
  • Bus Control (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Communication Control (AREA)
  • Computer And Data Communications (AREA)
  • Measuring Fluid Pressure (AREA)
AT03011314T 2002-05-20 2003-05-19 Verfahren und brückenelement-modul ATE376303T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/151,454 US6985991B2 (en) 2002-05-20 2002-05-20 Bridge element enabled module and method

Publications (1)

Publication Number Publication Date
ATE376303T1 true ATE376303T1 (de) 2007-11-15

Family

ID=29400509

Family Applications (1)

Application Number Title Priority Date Filing Date
AT03011314T ATE376303T1 (de) 2002-05-20 2003-05-19 Verfahren und brückenelement-modul

Country Status (6)

Country Link
US (1) US6985991B2 (de)
EP (1) EP1365544B1 (de)
JP (1) JP2003345736A (de)
AT (1) ATE376303T1 (de)
CA (1) CA2428414A1 (de)
DE (1) DE60316866T2 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050246474A1 (en) * 2004-04-29 2005-11-03 Wolfe Sarah M Monolithic VMEbus backplane having VME bridge module
US7620047B2 (en) * 2004-11-23 2009-11-17 Emerson Network Power - Embedded Computing, Inc. Method of transporting a RapidIO packet over an IP packet network
US7120725B2 (en) * 2004-11-23 2006-10-10 Motorola, Inc. Method of communicating a VMEbus signal over IP packet network
JP4810409B2 (ja) * 2006-11-29 2011-11-09 株式会社東芝 Ｖｍｅボード及びｃｒ／ｃｓｒレジスタのアクセス検知方法
DE102009002281A1 (de) * 2009-04-08 2010-10-14 Robert Bosch Gmbh Verfahren zur Anbindung von Slave-Karten an ein Bus-System
CN114980038B (zh) * 2021-02-24 2025-05-16 京东科技信息技术有限公司 机器人系统、用于数据通信的方法和装置
US12461878B2 (en) * 2021-12-22 2025-11-04 Intel Corporation System, method, apparatus and architecture for dynamically configuring device fabrics

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5414814A (en) * 1992-05-08 1995-05-09 The United States Of America As Represented By The Secretary Of The Navy I/O interface between VME bus and asynchronous serial data computer
US5796963A (en) * 1996-05-16 1998-08-18 National Instruments Corporation System and method for converting VXI bus cycles to PCI burst cycles
US6425033B1 (en) * 1997-06-20 2002-07-23 National Instruments Corporation System and method for connecting peripheral buses through a serial bus
US6175889B1 (en) * 1998-10-21 2001-01-16 Compaq Computer Corporation Apparatus, method and system for a computer CPU and memory to high speed peripheral interconnect bridge having a plurality of physical buses with a single logical bus number
DE19926849A1 (de) * 1999-06-11 2000-12-14 Bodenseewerk Geraetetech Datenübermittlung zwischen Modulen eines elektrischen Geräts
US6757762B1 (en) * 1999-10-29 2004-06-29 Unisys Corporation Multi-mode processor bus bridge

Also Published As

Publication number Publication date
DE60316866D1 (de) 2007-11-29
US6985991B2 (en) 2006-01-10
EP1365544B1 (de) 2007-10-17
US20030217217A1 (en) 2003-11-20
CA2428414A1 (en) 2003-11-20
DE60316866T2 (de) 2008-07-31
EP1365544A1 (de) 2003-11-26
JP2003345736A (ja) 2003-12-05

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Legal Events

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RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties