ATE382951T1 - Dünnschicht halbleiteranordnung, besonders leistungsanordnung, und verfahren zu deren herstellung - Google Patents

Dünnschicht halbleiteranordnung, besonders leistungsanordnung, und verfahren zu deren herstellung

Info

Publication number
ATE382951T1
ATE382951T1 AT03762728T AT03762728T ATE382951T1 AT E382951 T1 ATE382951 T1 AT E382951T1 AT 03762728 T AT03762728 T AT 03762728T AT 03762728 T AT03762728 T AT 03762728T AT E382951 T1 ATE382951 T1 AT E382951T1
Authority
AT
Austria
Prior art keywords
arrangement
production
thin film
film semiconductor
particular power
Prior art date
Application number
AT03762728T
Other languages
English (en)
Inventor
Laurent Clavelier
Eric Jalaguier
Original Assignee
Commissariat Energie Atomique
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat Energie Atomique filed Critical Commissariat Energie Atomique
Application granted granted Critical
Publication of ATE382951T1 publication Critical patent/ATE382951T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H10D12/032—Manufacture or treatment of IGBTs of vertical IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/20—Conductive package substrates serving as an interconnection, e.g. metal plates
    • H10W70/24—Conductive package substrates serving as an interconnection, e.g. metal plates characterised by materials
    • H10W70/26—Semiconductor materials
AT03762728T 2002-07-05 2003-07-02 Dünnschicht halbleiteranordnung, besonders leistungsanordnung, und verfahren zu deren herstellung ATE382951T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0208453A FR2842021B1 (fr) 2002-07-05 2002-07-05 Dispositif electronique, notamment dispositif de puissance, a couche mince, et procede de fabrication de ce dispositif

Publications (1)

Publication Number Publication Date
ATE382951T1 true ATE382951T1 (de) 2008-01-15

Family

ID=29725197

Family Applications (1)

Application Number Title Priority Date Filing Date
AT03762728T ATE382951T1 (de) 2002-07-05 2003-07-02 Dünnschicht halbleiteranordnung, besonders leistungsanordnung, und verfahren zu deren herstellung

Country Status (7)

Country Link
US (1) US20050242367A1 (de)
EP (1) EP1520294B1 (de)
JP (1) JP2005536041A (de)
AT (1) ATE382951T1 (de)
DE (1) DE60318445T2 (de)
FR (1) FR2842021B1 (de)
WO (1) WO2004006323A1 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10330571B8 (de) * 2003-07-07 2007-03-08 Infineon Technologies Ag Vertikale Leistungshalbleiterbauelemente mit Injektionsdämpfungsmittel im Rand bereich und Herstellungsverfahren dafür
US7419907B2 (en) * 2005-07-01 2008-09-02 International Business Machines Corporation Eliminating metal-rich silicides using an amorphous Ni alloy silicide structure
US7749877B2 (en) * 2006-03-07 2010-07-06 Siliconix Technology C. V. Process for forming Schottky rectifier with PtNi silicide Schottky barrier

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3925808A (en) * 1974-08-08 1975-12-09 Westinghouse Electric Corp Silicon semiconductor device with stress-free electrodes
US5643821A (en) * 1994-11-09 1997-07-01 Harris Corporation Method for making ohmic contact to lightly doped islands from a silicide buried layer and applications
US5897331A (en) * 1996-11-08 1999-04-27 Midwest Research Institute High efficiency low cost thin film silicon solar cell design and method for making
US6054369A (en) * 1997-06-30 2000-04-25 Intersil Corporation Lifetime control for semiconductor devices
US6104062A (en) * 1998-06-30 2000-08-15 Intersil Corporation Semiconductor device having reduced effective substrate resistivity and associated methods
DE19860581A1 (de) * 1998-12-29 2000-07-06 Asea Brown Boveri Halbleiterelement und Verfahren zur Herstellung
FR2798224B1 (fr) * 1999-09-08 2003-08-29 Commissariat Energie Atomique Realisation d'un collage electriquement conducteur entre deux elements semi-conducteurs.
US6630689B2 (en) * 2001-05-09 2003-10-07 Lumileds Lighting, U.S. Llc Semiconductor LED flip-chip with high reflectivity dielectric coating on the mesa
US7170176B2 (en) * 2003-11-04 2007-01-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device

Also Published As

Publication number Publication date
US20050242367A1 (en) 2005-11-03
EP1520294A1 (de) 2005-04-06
JP2005536041A (ja) 2005-11-24
DE60318445T2 (de) 2009-01-15
EP1520294B1 (de) 2008-01-02
DE60318445D1 (de) 2008-02-14
FR2842021B1 (fr) 2005-05-13
WO2004006323A1 (fr) 2004-01-15
FR2842021A1 (fr) 2004-01-09

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Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties