ATE386300T1 - Architektur eines kommunikationsknoten in einem global asynchronen netzwerk on-chip-system - Google Patents
Architektur eines kommunikationsknoten in einem global asynchronen netzwerk on-chip-systemInfo
- Publication number
- ATE386300T1 ATE386300T1 AT06110721T AT06110721T ATE386300T1 AT E386300 T1 ATE386300 T1 AT E386300T1 AT 06110721 T AT06110721 T AT 06110721T AT 06110721 T AT06110721 T AT 06110721T AT E386300 T1 ATE386300 T1 AT E386300T1
- Authority
- AT
- Austria
- Prior art keywords
- architecture
- communication node
- chip system
- asynchronous network
- hierarchy
- Prior art date
Links
- 230000005540 biological transmission Effects 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/42—Loop networks
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Communication Control (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR0550611A FR2883117B1 (fr) | 2005-03-08 | 2005-03-08 | Architecture de noeud de communication dans un systeme de reseau sur puce globalement asynchrone. |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ATE386300T1 true ATE386300T1 (de) | 2008-03-15 |
Family
ID=34954683
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AT06110721T ATE386300T1 (de) | 2005-03-08 | 2006-03-06 | Architektur eines kommunikationsknoten in einem global asynchronen netzwerk on-chip-system |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US7940666B2 (de) |
| EP (1) | EP1701274B8 (de) |
| JP (1) | JP4808514B2 (de) |
| AT (1) | ATE386300T1 (de) |
| DE (1) | DE602006000516T2 (de) |
| FR (1) | FR2883117B1 (de) |
Families Citing this family (42)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010500641A (ja) * | 2006-08-08 | 2010-01-07 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | 電子装置及び通信同期方法 |
| US20090067343A1 (en) * | 2007-06-04 | 2009-03-12 | David Fritz | Method for the synthesis of optimal asynchronous on-chip communication networks from system-level constraints |
| WO2008149784A1 (ja) | 2007-06-08 | 2008-12-11 | Nec Corporation | 半導体集積回路及びフィルタ制御方法 |
| WO2008149783A1 (ja) * | 2007-06-08 | 2008-12-11 | Nec Corporation | 半導体集積回路及びフィルタ制御方法 |
| US7783823B2 (en) * | 2007-07-31 | 2010-08-24 | Hewlett-Packard Development Company, L.P. | Hardware device data buffer |
| EP2026493A1 (de) * | 2007-08-16 | 2009-02-18 | STMicroelectronics S.r.l. | Verfahren und System für mesochrone Kommunikationen in mehreren Taktdomänen und entsprechendes Computerprogrammprodukt |
| US8261025B2 (en) | 2007-11-12 | 2012-09-04 | International Business Machines Corporation | Software pipelining on a network on chip |
| US8526422B2 (en) | 2007-11-27 | 2013-09-03 | International Business Machines Corporation | Network on chip with partitions |
| FR2925187B1 (fr) * | 2007-12-14 | 2011-04-08 | Commissariat Energie Atomique | Systeme comportant une pluralite d'unites de traitement permettant d'executer des taches en parallele,en mixant le mode d'execution de type controle et le mode d'execution de type flot de donnees |
| US8473667B2 (en) * | 2008-01-11 | 2013-06-25 | International Business Machines Corporation | Network on chip that maintains cache coherency with invalidation messages |
| US8490110B2 (en) | 2008-02-15 | 2013-07-16 | International Business Machines Corporation | Network on chip with a low latency, high bandwidth application messaging interconnect |
| US8638665B2 (en) | 2008-04-30 | 2014-01-28 | Nec Corporation | Router, information processing device having said router, and packet routing method |
| US8423715B2 (en) | 2008-05-01 | 2013-04-16 | International Business Machines Corporation | Memory management among levels of cache in a memory hierarchy |
| US8494833B2 (en) | 2008-05-09 | 2013-07-23 | International Business Machines Corporation | Emulating a computer run time environment |
| US8214845B2 (en) * | 2008-05-09 | 2012-07-03 | International Business Machines Corporation | Context switching in a network on chip by thread saving and restoring pointers to memory arrays containing valid message data |
| US8392664B2 (en) | 2008-05-09 | 2013-03-05 | International Business Machines Corporation | Network on chip |
| US8230179B2 (en) * | 2008-05-15 | 2012-07-24 | International Business Machines Corporation | Administering non-cacheable memory load instructions |
| US8040799B2 (en) * | 2008-05-15 | 2011-10-18 | International Business Machines Corporation | Network on chip with minimum guaranteed bandwidth for virtual communications channels |
| US8438578B2 (en) | 2008-06-09 | 2013-05-07 | International Business Machines Corporation | Network on chip with an I/O accelerator |
| US8131975B1 (en) | 2008-07-07 | 2012-03-06 | Ovics | Matrix processor initialization systems and methods |
| US8327114B1 (en) * | 2008-07-07 | 2012-12-04 | Ovics | Matrix processor proxy systems and methods |
| US8145880B1 (en) | 2008-07-07 | 2012-03-27 | Ovics | Matrix processor data switch routing systems and methods |
| US7958341B1 (en) | 2008-07-07 | 2011-06-07 | Ovics | Processing stream instruction in IC of mesh connected matrix of processors containing pipeline coupled switch transferring messages over consecutive cycles from one link to another link or memory |
| US8195884B2 (en) | 2008-09-18 | 2012-06-05 | International Business Machines Corporation | Network on chip with caching restrictions for pages of computer memory |
| DE102008049620A1 (de) * | 2008-09-30 | 2010-04-01 | Bayerische Motoren Werke Aktiengesellschaft | Kommunikationssystem |
| US8108908B2 (en) | 2008-10-22 | 2012-01-31 | International Business Machines Corporation | Security methodology to prevent user from compromising throughput in a highly threaded network on a chip processor |
| JP5307525B2 (ja) * | 2008-12-03 | 2013-10-02 | キヤノン株式会社 | データ処理装置及びその制御方法 |
| US8509078B2 (en) * | 2009-02-12 | 2013-08-13 | Microsoft Corporation | Bufferless routing in on-chip interconnection networks |
| DE102009002007B3 (de) * | 2009-03-31 | 2010-07-01 | Robert Bosch Gmbh | Netzwerkcontroller in einem Netzwerk, Netzwerk und Routingverfahren für Nachrichten in einem Netzwerk |
| FR2948840B1 (fr) | 2009-07-29 | 2011-09-16 | Kalray | Reseau de communication sur puce avec garantie de service |
| FR2949879B1 (fr) | 2009-09-04 | 2014-07-18 | Kalray | Noeuds d'entree/sortie d'un reseau sur puce torique. |
| FR2951868B1 (fr) | 2009-10-28 | 2012-04-06 | Kalray | Briques de construction d'un reseau sur puce |
| FR2957176B1 (fr) * | 2010-03-02 | 2012-04-06 | Commissariat Energie Atomique | Puce electronique et circuit integre comportant une telle puce electronique |
| WO2012029215A1 (ja) * | 2010-09-03 | 2012-03-08 | パナソニック株式会社 | 中継装置 |
| JP2012146201A (ja) * | 2011-01-13 | 2012-08-02 | Toshiba Corp | オンチップルータ及びそれを用いたマルチコアシステム |
| JP2012186539A (ja) * | 2011-03-03 | 2012-09-27 | Renesas Electronics Corp | ルータ装置、ルータ装置の制御方法 |
| WO2012125718A1 (en) * | 2011-03-16 | 2012-09-20 | The Trustees Of Columbia University In The City Of New York | Bi-modal arbitration nodes for a low-latency adaptive asynchronous interconnection network and methods for using the same |
| CN102158403B (zh) * | 2011-03-24 | 2014-03-05 | 山东大学 | 一种适用于片上网络的高效数据流传输通信系统及其工作方法 |
| CN103348640B (zh) * | 2011-07-22 | 2016-11-23 | 松下知识产权经营株式会社 | 中继装置 |
| JP2013196167A (ja) | 2012-03-16 | 2013-09-30 | Toshiba Corp | 情報処理装置 |
| US12034570B2 (en) | 2022-03-14 | 2024-07-09 | T-Mobile Usa, Inc. | Multi-element routing system for mobile communications |
| US12058029B2 (en) * | 2022-10-14 | 2024-08-06 | Google Llc | Virtual channel balancing in ring-based topologies |
Family Cites Families (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5812534A (en) * | 1993-01-08 | 1998-09-22 | Multi-Tech Systems, Inc. | Voice over data conferencing for a computer-based personal communications system |
| JP4326700B2 (ja) * | 1998-08-20 | 2009-09-09 | クゥアルコム・インコーポレイテッド | セルラ電話システム中の優先アクセスチャネル割当のためのシステムおよび方法 |
| US6859454B1 (en) * | 1999-06-30 | 2005-02-22 | Broadcom Corporation | Network switch with high-speed serializing/deserializing hazard-free double data rate switching |
| DE60128413T2 (de) * | 2000-03-02 | 2008-01-17 | Alcatel Lucent | Gekennzeichneter Prioritätswarteschlangescheduler |
| US6917589B2 (en) * | 2001-01-25 | 2005-07-12 | Agere Systems Inc. | Automatic quality of service assignment in ethernet switches |
| US7283557B2 (en) | 2002-01-25 | 2007-10-16 | Fulcrum Microsystems, Inc. | Asynchronous crossbar with deterministic or arbitrated control |
| DE60314935T2 (de) * | 2002-04-16 | 2007-12-20 | Robert Bosch Gmbh | Verfahren und Einheit zur Bitstromdekodierung |
| US7277449B2 (en) * | 2002-07-29 | 2007-10-02 | Freescale Semiconductor, Inc. | On chip network |
| US20040090964A1 (en) * | 2002-11-07 | 2004-05-13 | Coke Reed | Means and apparatus for a scaleable congestion free switching system with intelligent control II |
| DE10252536A1 (de) * | 2002-11-08 | 2004-05-27 | Philips Intellectual Property & Standards Gmbh | Verfahren und Vorrichtung zur Übertragung von Datenpaketen |
| WO2005106687A1 (en) * | 2004-04-28 | 2005-11-10 | Koninklijke Philips Electronics N.V. | Circuit with asynchronous/synchronous interface |
| US20080144493A1 (en) * | 2004-06-30 | 2008-06-19 | Chi-Hsiang Yeh | Method of interference management for interference/collision prevention/avoidance and spatial reuse enhancement |
| CN101002443A (zh) * | 2004-08-12 | 2007-07-18 | 皇家飞利浦电子股份有限公司 | 用于在集成电路中将数据分配给至少一个分组的方法 |
| US20060190852A1 (en) * | 2005-01-12 | 2006-08-24 | Sotiriou Christos P | Asynchronous, multi-rail, asymmetric-phase, static digital logic with completion detection and method for designing the same |
| US7535907B2 (en) * | 2005-04-08 | 2009-05-19 | Oavium Networks, Inc. | TCP engine |
-
2005
- 2005-03-08 FR FR0550611A patent/FR2883117B1/fr not_active Expired - Lifetime
-
2006
- 2006-03-06 AT AT06110721T patent/ATE386300T1/de not_active IP Right Cessation
- 2006-03-06 EP EP06110721A patent/EP1701274B8/de not_active Expired - Lifetime
- 2006-03-06 DE DE602006000516T patent/DE602006000516T2/de not_active Expired - Lifetime
- 2006-03-08 US US11/372,296 patent/US7940666B2/en active Active
- 2006-03-08 JP JP2006062182A patent/JP4808514B2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| US20060203825A1 (en) | 2006-09-14 |
| US7940666B2 (en) | 2011-05-10 |
| EP1701274B8 (de) | 2008-07-16 |
| EP1701274A1 (de) | 2006-09-13 |
| JP2006254450A (ja) | 2006-09-21 |
| DE602006000516D1 (de) | 2008-03-27 |
| FR2883117B1 (fr) | 2007-04-27 |
| JP4808514B2 (ja) | 2011-11-02 |
| EP1701274B1 (de) | 2008-02-13 |
| FR2883117A1 (fr) | 2006-09-15 |
| DE602006000516T2 (de) | 2009-04-02 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |