ATE390820T1 - Elektrische räumschaltmatrix - Google Patents

Elektrische räumschaltmatrix

Info

Publication number
ATE390820T1
ATE390820T1 AT03360014T AT03360014T ATE390820T1 AT E390820 T1 ATE390820 T1 AT E390820T1 AT 03360014 T AT03360014 T AT 03360014T AT 03360014 T AT03360014 T AT 03360014T AT E390820 T1 ATE390820 T1 AT E390820T1
Authority
AT
Austria
Prior art keywords
matrix
inputs
outputs
chip
switch matrix
Prior art date
Application number
AT03360014T
Other languages
English (en)
Inventor
Helmut Preisach
Original Assignee
Alcatel Lucent
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel Lucent filed Critical Alcatel Lucent
Application granted granted Critical
Publication of ATE390820T1 publication Critical patent/ATE390820T1/de

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H04L49/101—Packet switching elements characterised by the switching fabric construction using crossbar or matrix
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/15—Interconnection of switching modules
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
    • H04Q11/0005—Switch and router aspects
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
    • H04Q11/0005—Switch and router aspects
    • H04Q2011/0037—Operation
    • H04Q2011/0045—Synchronisation

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
  • Electronic Switches (AREA)
  • Studio Circuits (AREA)
  • Saccharide Compounds (AREA)
AT03360014T 2003-02-05 2003-02-05 Elektrische räumschaltmatrix ATE390820T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP03360014A EP1445974B1 (de) 2003-02-05 2003-02-05 Elektrische Räumschaltmatrix

Publications (1)

Publication Number Publication Date
ATE390820T1 true ATE390820T1 (de) 2008-04-15

Family

ID=32605455

Family Applications (1)

Application Number Title Priority Date Filing Date
AT03360014T ATE390820T1 (de) 2003-02-05 2003-02-05 Elektrische räumschaltmatrix

Country Status (4)

Country Link
US (1) US8305111B2 (de)
EP (1) EP1445974B1 (de)
AT (1) ATE390820T1 (de)
DE (1) DE60319945T2 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009134573A (ja) * 2007-11-30 2009-06-18 Nec Corp マルチチップ半導体装置およびデータ転送方法
US10141926B2 (en) 2016-07-19 2018-11-27 Ciena Corporation Ultra-low power cross-point electronic switch apparatus and method
TWI806145B (zh) * 2021-09-02 2023-06-21 立積電子股份有限公司 開關電路之結構及其佈線系統

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5319261A (en) * 1992-07-30 1994-06-07 Aptix Corporation Reprogrammable interconnect architecture using fewer storage cells than switches
US5396126A (en) * 1993-02-19 1995-03-07 At&T Corp. FPGA with distributed switch matrix
US5436576A (en) * 1994-05-20 1995-07-25 Intel Corporation Switch matrices using reduced number of switching devices for signal routing
US5850564A (en) * 1995-05-03 1998-12-15 Btr, Inc, Scalable multiple level tab oriented interconnect architecture
JP3486725B2 (ja) * 1995-11-28 2004-01-13 株式会社ルネサステクノロジ 可変論理集積回路
US6545505B1 (en) * 1997-09-30 2003-04-08 Cypress Semiconductor Corporation Hybrid routing architecture for high density complex programmable logic devices
JP3391374B2 (ja) * 1998-12-25 2003-03-31 富士通株式会社 クロスポイントスイッチ回路および基本スイッチセル電子回路
US6362650B1 (en) * 2000-05-18 2002-03-26 Xilinx, Inc. Method and apparatus for incorporating a multiplier into an FPGA
US6515509B1 (en) * 2000-07-13 2003-02-04 Xilinx, Inc. Programmable logic device structures in standard cell devices
US6844757B2 (en) * 2002-06-28 2005-01-18 Lattice Semiconductor Corp. Converting bits to vectors in a programmable logic device

Also Published As

Publication number Publication date
US8305111B2 (en) 2012-11-06
DE60319945D1 (de) 2008-05-08
DE60319945T2 (de) 2008-07-17
EP1445974B1 (de) 2008-03-26
EP1445974A1 (de) 2004-08-11
US20040150008A1 (en) 2004-08-05

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Legal Events

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