ATE406698T1 - Anwenderprogrammierbare gatterfelder (fpga) und verfahren zur bearbeitung von fpga- konfigurationsdaten - Google Patents

Anwenderprogrammierbare gatterfelder (fpga) und verfahren zur bearbeitung von fpga- konfigurationsdaten

Info

Publication number
ATE406698T1
ATE406698T1 AT00305632T AT00305632T ATE406698T1 AT E406698 T1 ATE406698 T1 AT E406698T1 AT 00305632 T AT00305632 T AT 00305632T AT 00305632 T AT00305632 T AT 00305632T AT E406698 T1 ATE406698 T1 AT E406698T1
Authority
AT
Austria
Prior art keywords
fpga
configuration data
volatile
encrypted
memory
Prior art date
Application number
AT00305632T
Other languages
English (en)
Inventor
Paul Jeffrey Garnett
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Application granted granted Critical
Publication of ATE406698T1 publication Critical patent/ATE406698T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/76—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/1776—Structural details of configuration resources for memories
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/17768—Structural details of configuration resources for security

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Computing Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Software Systems (AREA)
  • General Physics & Mathematics (AREA)
  • Logic Circuits (AREA)
  • Storage Device Security (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
AT00305632T 2000-07-04 2000-07-04 Anwenderprogrammierbare gatterfelder (fpga) und verfahren zur bearbeitung von fpga- konfigurationsdaten ATE406698T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP00305632A EP1170868B1 (de) 2000-07-04 2000-07-04 Anwenderprogrammierbare Gatterfelder (FPGA) und Verfahren zur Bearbeitung von FPGA-Konfigurationsdaten

Publications (1)

Publication Number Publication Date
ATE406698T1 true ATE406698T1 (de) 2008-09-15

Family

ID=8173100

Family Applications (1)

Application Number Title Priority Date Filing Date
AT00305632T ATE406698T1 (de) 2000-07-04 2000-07-04 Anwenderprogrammierbare gatterfelder (fpga) und verfahren zur bearbeitung von fpga- konfigurationsdaten

Country Status (3)

Country Link
EP (1) EP1170868B1 (de)
AT (1) ATE406698T1 (de)
DE (1) DE60040064D1 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7260218B2 (en) 2005-11-08 2007-08-21 M2000 Configurable circuit with configuration data protection features
WO2007120439A2 (en) * 2006-04-14 2007-10-25 Raytheon Company Data storing
DE102006045372A1 (de) * 2006-09-26 2008-04-03 Rohde & Schwarz Sit Gmbh Verfahren und Vorrichtung zum Erzeugen und Zuführen von Konfigurationsdaten für bzw. in eine programmierbare, integrierte Logikschaltung
US8117137B2 (en) 2007-04-19 2012-02-14 Microsoft Corporation Field-programmable gate array based accelerator system
US8627079B2 (en) 2007-11-01 2014-01-07 Infineon Technologies Ag Method and system for controlling a device
US20100031026A1 (en) * 2007-11-01 2010-02-04 Infineon Technologies North America Corp. Method and system for transferring information to a device
US8908870B2 (en) 2007-11-01 2014-12-09 Infineon Technologies Ag Method and system for transferring information to a device
US8402536B2 (en) 2008-04-15 2013-03-19 Nokia Corporation Signature based authentication of the configuration of a configurable logic component
FR2935078B1 (fr) * 2008-08-12 2012-11-16 Groupe Des Ecoles De Telecommunications Get Ecole Nationale Superieure Des Telecommunications Enst Procede de protection du decryptage des fichiers de configuration de circuits logiques programmables et circuit mettant en oeuvre le procede
US8131659B2 (en) 2008-09-25 2012-03-06 Microsoft Corporation Field-programmable gate array based accelerator system
US8301638B2 (en) 2008-09-25 2012-10-30 Microsoft Corporation Automated feature selection based on rankboost for ranking
CN103873227A (zh) * 2012-12-13 2014-06-18 艺伦半导体技术股份有限公司 一种fpga加密数据流的解密电路及解密方法
US10708073B2 (en) * 2016-11-08 2020-07-07 Honeywell International Inc. Configuration based cryptographic key generation
US10438022B2 (en) * 2016-12-16 2019-10-08 Arm Limited Logic encryption using on-chip memory cells
FI128520B (en) * 2018-11-14 2020-07-15 Xiphera Oy A method for generating a secret unique key for a volatile memory FPGA
CN114462105A (zh) * 2022-03-18 2022-05-10 浙江中控研究院有限公司 一种应用于现场可编程逻辑门阵列的程序防盗方法及装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB9121591D0 (en) * 1991-10-11 1991-11-27 Pilkington Micro Electronics Data security arrangement for semiconductor programmable logic devices
US5768372A (en) * 1996-03-13 1998-06-16 Altera Corporation Method and apparatus for securing programming data of a programmable logic device
US5970142A (en) * 1996-08-26 1999-10-19 Xilinx, Inc. Configuration stream encryption
US6150837A (en) * 1997-02-28 2000-11-21 Actel Corporation Enhanced field programmable gate array
US6118869A (en) * 1998-03-11 2000-09-12 Xilinx, Inc. System and method for PLD bitstream encryption
US6654889B1 (en) * 1999-02-19 2003-11-25 Xilinx, Inc. Method and apparatus for protecting proprietary configuration data for programmable logic devices

Also Published As

Publication number Publication date
EP1170868B1 (de) 2008-08-27
DE60040064D1 (de) 2008-10-09
EP1170868A1 (de) 2002-01-09

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