ATE409916T1 - Programmierbare pipeline-matrix mit teilweise globalen konfigurationsbussen - Google Patents

Programmierbare pipeline-matrix mit teilweise globalen konfigurationsbussen

Info

Publication number
ATE409916T1
ATE409916T1 AT03788452T AT03788452T ATE409916T1 AT E409916 T1 ATE409916 T1 AT E409916T1 AT 03788452 T AT03788452 T AT 03788452T AT 03788452 T AT03788452 T AT 03788452T AT E409916 T1 ATE409916 T1 AT E409916T1
Authority
AT
Austria
Prior art keywords
stripes
stripe
virtual
physical
processing elements
Prior art date
Application number
AT03788452T
Other languages
English (en)
Inventor
Herman Schmit
Original Assignee
Univ Carnegie Mellon
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Univ Carnegie Mellon filed Critical Univ Carnegie Mellon
Application granted granted Critical
Publication of ATE409916T1 publication Critical patent/ATE409916T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3893—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator
    • G06F9/3895—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros
    • G06F9/3897—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros with adaptable data path
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Logic Circuits (AREA)
  • Storage Device Security (AREA)
  • Advance Control (AREA)
  • Image Processing (AREA)
AT03788452T 2002-08-16 2003-08-14 Programmierbare pipeline-matrix mit teilweise globalen konfigurationsbussen ATE409916T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/222,645 US7263602B2 (en) 2002-08-16 2002-08-16 Programmable pipeline fabric utilizing partially global configuration buses

Publications (1)

Publication Number Publication Date
ATE409916T1 true ATE409916T1 (de) 2008-10-15

Family

ID=31715027

Family Applications (1)

Application Number Title Priority Date Filing Date
AT03788452T ATE409916T1 (de) 2002-08-16 2003-08-14 Programmierbare pipeline-matrix mit teilweise globalen konfigurationsbussen

Country Status (8)

Country Link
US (1) US7263602B2 (de)
EP (1) EP1535189B1 (de)
JP (1) JP2005539293A (de)
CN (1) CN100392635C (de)
AT (1) ATE409916T1 (de)
AU (1) AU2003262645A1 (de)
DE (1) DE60323847D1 (de)
WO (1) WO2004017223A2 (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4546775B2 (ja) * 2004-06-30 2010-09-15 富士通株式会社 時分割多重処理可能なリコンフィギュラブル回路
JP4547198B2 (ja) * 2004-06-30 2010-09-22 富士通株式会社 演算装置、演算装置の制御方法、プログラム及びコンピュータ読取り可能記録媒体
KR100662873B1 (ko) * 2006-01-03 2007-01-02 삼성전자주식회사 루프가속기 및 이를 포함하는 데이터 처리 시스템
EP2352082B1 (de) * 2008-10-14 2018-11-28 National University Corporation Nara Institute of Science and Technology Datenverarbeitungseinrichtung zur parallelen durchführung von mehreren rechenprozessen
JP5552855B2 (ja) 2010-03-19 2014-07-16 富士ゼロックス株式会社 画像処理装置、画像形成システム及び画像処理プログラム
GB2535547B (en) * 2015-04-21 2017-01-11 Adaptive Array Systems Ltd Data processor
WO2019089816A2 (en) 2017-10-31 2019-05-09 Micron Technology, Inc. System having a hybrid threading processor, a hybrid threading fabric having configurable computing elements, and a hybrid interconnection network
CN111919204B (zh) 2018-03-31 2024-12-10 美光科技公司 用于多线程自调度可重新配置计算架构高效循环执行
EP3776188B1 (de) 2018-03-31 2025-04-30 Micron Technology, Inc. Bedingte verzweigungssteuerung für eine selbstplanende rekonfigurierbare multithread-rechenmatrix
KR102446709B1 (ko) 2018-03-31 2022-09-26 마이크론 테크놀로지, 인크. 멀티 스레드, 자체 스케줄링 재구성 가능한 컴퓨팅 패브릭의 실행 제어
EP3776243B1 (de) 2018-03-31 2025-01-01 Micron Technology, Inc. Gegendrucksteuerung unter verwendung eines stoppsignals für eine rekonfigurierbare rechnerstruktur mit mehreren threads und eigenständiger planung
CN111919207B (zh) 2018-03-31 2025-02-28 美光科技公司 多线程自调度可重新配置计算架构
WO2019191744A1 (en) 2018-03-31 2019-10-03 Micron Technology, Inc. Loop execution control for a multi-threaded, self-scheduling reconfigurable computing fabric using a reenter queue
EP3776237A1 (de) 2018-03-31 2021-02-17 Micron Technology, Inc. Mehrfache arten von thread-identifikatoren für eine selbstplanende rekonfigurierbare multithread-rechenmatrix
WO2019191742A1 (en) 2018-03-31 2019-10-03 Micron Technology, Inc. Loop thread order execution control of a multi-threaded, self-scheduling reconfigurable computing fabric
US11573834B2 (en) 2019-08-22 2023-02-07 Micron Technology, Inc. Computational partition for a multi-threaded, self-scheduling reconfigurable computing fabric
US11150900B2 (en) 2019-08-28 2021-10-19 Micron Technology, Inc. Execution or write mask generation for data selection in a multi-threaded, self-scheduling reconfigurable computing fabric
US11886377B2 (en) 2019-09-10 2024-01-30 Cornami, Inc. Reconfigurable arithmetic engine circuit
CN116521134A (zh) * 2023-03-13 2023-08-01 广州嘉为科技有限公司 在ci流水线执行过程中修改其参数的方法、装置及介质

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5684980A (en) * 1992-07-29 1997-11-04 Virtual Computer Corporation FPGA virtual computer for executing a sequence of program instructions by successively reconfiguring a group of FPGA in response to those instructions
JP3308770B2 (ja) * 1994-07-22 2002-07-29 三菱電機株式会社 情報処理装置および情報処理装置における計算方法
US5794062A (en) * 1995-04-17 1998-08-11 Ricoh Company Ltd. System and method for dynamically reconfigurable computing using a processing unit having changeable internal hardware organization
JPH09106389A (ja) * 1995-10-12 1997-04-22 Sony Corp 信号処理装置
FI971718L (fi) * 1997-04-22 1998-10-23 Nokia Telecommunications Oy Korttipaikkojen lisääminen suurikapasiteettiseen väylään
US6167502A (en) * 1997-10-10 2000-12-26 Billions Of Operations Per Second, Inc. Method and apparatus for manifold array processing
JPH11259436A (ja) * 1998-03-10 1999-09-24 Toppan Printing Co Ltd データ並列処理方法
US6119215A (en) * 1998-06-29 2000-09-12 Cisco Technology, Inc. Synchronization and control system for an arrayed processing engine
US6442732B1 (en) * 1999-04-21 2002-08-27 Lucent Technologies, Inc. Virtual logic system for solving satisfiability problems using reconfigurable hardware
ATE498158T1 (de) * 2000-11-06 2011-02-15 Broadcom Corp Umkonfigurierbares verarbeitungssystem und - verfahren
CN1156760C (zh) * 2000-12-12 2004-07-07 智原科技股份有限公司 适用于处理器的存储器数据存取装置及其存取方法
US6526559B2 (en) * 2001-04-13 2003-02-25 Interface & Control Systems, Inc. Method for creating circuit redundancy in programmable logic devices

Also Published As

Publication number Publication date
WO2004017223A3 (en) 2004-04-08
EP1535189A2 (de) 2005-06-01
CN100392635C (zh) 2008-06-04
AU2003262645A8 (en) 2004-03-03
DE60323847D1 (de) 2008-11-13
WO2004017223A2 (en) 2004-02-26
US20040034761A1 (en) 2004-02-19
AU2003262645A1 (en) 2004-03-03
JP2005539293A (ja) 2005-12-22
EP1535189B1 (de) 2008-10-01
US7263602B2 (en) 2007-08-28
CN1688991A (zh) 2005-10-26

Similar Documents

Publication Publication Date Title
DE60323847D1 (de) Programmierbare pipeline-matrix mit teilweise globalen konfigurationsbussen
US7394284B2 (en) Reconfigurable sequencer structure
US6449628B1 (en) Apparatus and method for programmable datapath arithmetic arrays
US7765382B2 (en) Propagating reconfiguration command over asynchronous self-synchronous global and inter-cluster local buses coupling wrappers of clusters of processing module matrix
EP4321993A3 (de) Programmierbare matrixverarbeitungsmaschine
WO2004042561A3 (en) Pipeline accelerator having multiple pipeline units and related computing machine and method
WO2008084363A3 (en) Circuit comprising a matrix of programmable logic cells
HUP0301274A2 (en) Block based design methodology
WO2004003781A3 (en) Processing system with interspersed processors and communication elements
WO2005073866A3 (en) Systems and methods for reconfigurable computing
WO2005024644A3 (en) Integrated data processing circuit with a plurality of programmable processors
WO2005088454A3 (en) Processing pipeline with progressive cache
Bisasky et al. A many-core platform implemented for multi-channel seizure detection
ATE456091T1 (de) Schnelles redundantes datenverarbeitungssystem
US20160315620A1 (en) An extensible and configurable logic element, and an fpga device
EP4052373A1 (de) Konfigurationsspeichersystem für programmierbare vorrichtung
US7545196B1 (en) Clock distribution for specialized processing block in programmable logic device
US11429459B2 (en) Broadcasting event messages in a System on Chip using a crosslinked tree structure
US7890913B1 (en) Wire mapping for programmable logic devices
CN209118339U (zh) 加速器、基于fpga的加速系统及cnn网络系统
US20160085449A1 (en) Managing memory in a multiprocessor system
CN107885690A (zh) Spi交换系统及其控制方法
CN105260334B (zh) 仲裁和多路复用电路系统
Papadimitriou et al. Methodology and experimental setup for the determination of system-level dynamic reconfiguration overhead
TW200835151A (en) Low-power dynamic sequential controlling multiplexer

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties