ATE414300T1 - Mechanismus zur speichersequestrierung für busgeräte - Google Patents

Mechanismus zur speichersequestrierung für busgeräte

Info

Publication number
ATE414300T1
ATE414300T1 AT05760595T AT05760595T ATE414300T1 AT E414300 T1 ATE414300 T1 AT E414300T1 AT 05760595 T AT05760595 T AT 05760595T AT 05760595 T AT05760595 T AT 05760595T AT E414300 T1 ATE414300 T1 AT E414300T1
Authority
AT
Austria
Prior art keywords
memory
bus
coupled
bus devices
control device
Prior art date
Application number
AT05760595T
Other languages
English (en)
Inventor
David Durham
Priya Rajagopal
Ravi Sahita
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of ATE414300T1 publication Critical patent/ATE414300T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0284—Multiple user address space allocation, e.g. using different base addresses

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Storage Device Security (AREA)
  • Multi Processors (AREA)
  • Exchange Systems With Centralized Control (AREA)
  • Stringed Musical Instruments (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
AT05760595T 2004-06-24 2005-06-10 Mechanismus zur speichersequestrierung für busgeräte ATE414300T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/876,190 US20050289316A1 (en) 2004-06-24 2004-06-24 Mechanism for sequestering memory for a bus device

Publications (1)

Publication Number Publication Date
ATE414300T1 true ATE414300T1 (de) 2008-11-15

Family

ID=34972541

Family Applications (1)

Application Number Title Priority Date Filing Date
AT05760595T ATE414300T1 (de) 2004-06-24 2005-06-10 Mechanismus zur speichersequestrierung für busgeräte

Country Status (7)

Country Link
US (1) US20050289316A1 (de)
EP (1) EP1759295B1 (de)
CN (1) CN1957334B (de)
AT (1) ATE414300T1 (de)
DE (1) DE602005011005D1 (de)
TW (1) TWI293413B (de)
WO (1) WO2006011958A1 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7870565B2 (en) * 2005-06-30 2011-01-11 Intel Corporation Systems and methods for secure host resource management
US7941813B1 (en) 2006-02-17 2011-05-10 Parallels Holdings, Ltd. System and method for using virtual machine for driver installation sandbox
CN104335220B (zh) * 2012-03-30 2018-04-20 爱迪德技术有限公司 用于防止和检测安全威胁的方法和系统
GB2540961B (en) * 2015-07-31 2019-09-18 Arm Ip Ltd Controlling configuration data storage
TWI832612B (zh) * 2022-12-14 2024-02-11 精拓科技股份有限公司 I2c通訊系統的目標從屬裝置及其位址更新方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6226729B1 (en) * 1998-11-03 2001-05-01 Intel Corporation Method and apparatus for configuring and initializing a memory device and a memory channel
US6438671B1 (en) * 1999-07-01 2002-08-20 International Business Machines Corporation Generating partition corresponding real address in partitioned mode supporting system
TW528948B (en) * 2000-09-14 2003-04-21 Intel Corp Memory module having buffer for isolating stacked memory devices
US6748512B2 (en) * 2000-12-08 2004-06-08 Intel Corporation Method and apparatus for mapping address space of integrated programmable devices within host system memory
US6792505B2 (en) * 2001-04-16 2004-09-14 International Business Machines Corporation System apparatus and method for storage device controller-based message passing having effective data channel bandwidth and controller cache memory increase
US6792515B2 (en) * 2001-06-21 2004-09-14 International Business Machines Corporation System for addressing processors connected to a peripheral bus
US20030097503A1 (en) * 2001-11-19 2003-05-22 Huckins Jeffrey L. PCI compatible bus model for non-PCI compatible bus architectures
US7003586B1 (en) * 2002-02-27 2006-02-21 Advanced Micro Devices, Inc. Arrangement for implementing kernel bypass for access by user mode consumer processes to a channel adapter based on virtual address mapping
US20050166011A1 (en) * 2004-01-23 2005-07-28 Burnett Robert J. System for consolidating disk storage space of grid computers into a single virtual disk drive

Also Published As

Publication number Publication date
EP1759295B1 (de) 2008-11-12
HK1095185A1 (en) 2007-04-27
TWI293413B (en) 2008-02-11
EP1759295A1 (de) 2007-03-07
CN1957334B (zh) 2011-03-30
WO2006011958A1 (en) 2006-02-02
US20050289316A1 (en) 2005-12-29
TW200617673A (en) 2006-06-01
DE602005011005D1 (de) 2008-12-24
CN1957334A (zh) 2007-05-02

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Legal Events

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