ATE415742T1 - DATA TRANSMISSION SYSTEM AND METHOD IN AN ELECTRONIC CIRCUIT - Google Patents

DATA TRANSMISSION SYSTEM AND METHOD IN AN ELECTRONIC CIRCUIT

Info

Publication number
ATE415742T1
ATE415742T1 AT05291515T AT05291515T ATE415742T1 AT E415742 T1 ATE415742 T1 AT E415742T1 AT 05291515 T AT05291515 T AT 05291515T AT 05291515 T AT05291515 T AT 05291515T AT E415742 T1 ATE415742 T1 AT E415742T1
Authority
AT
Austria
Prior art keywords
electronic circuit
lines
transmission lines
data transmission
transmission system
Prior art date
Application number
AT05291515T
Other languages
German (de)
Inventor
Luc Montperrus
Original Assignee
Arteris
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Arteris filed Critical Arteris
Application granted granted Critical
Publication of ATE415742T1 publication Critical patent/ATE415742T1/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B3/00—Line transmission systems
    • H04B3/02—Details
    • H04B3/32—Reducing cross-talk, e.g. by compensating
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/08—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2205/00—Indexing scheme relating to group G06F5/00; Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F2205/10—Indexing scheme relating to groups G06F5/10 - G06F5/14
    • G06F2205/104—Delay lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dc Digital Transmission (AREA)
  • Communication Control (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Radar Systems Or Details Thereof (AREA)

Abstract

The system has signal transmission lines, each including inverting and non-inverting signal regeneration units (I, N). The transmission lines have four subsets of lines (ss ens1-ss ens4), each comprising a transmission line equipped with a periodical arrangement of the regeneration units, where the regeneration units are arranged in a plane perpendicular to the transmission lines. Four successive transmission lines arranged at the same level in a constant order belong respectively to a distinct subset among the subsets of lines. An independent claim is also included for a method for transferring data in an electronic circuit.
AT05291515T 2005-06-10 2005-07-13 DATA TRANSMISSION SYSTEM AND METHOD IN AN ELECTRONIC CIRCUIT ATE415742T1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0505896A FR2887093B1 (en) 2005-06-10 2005-06-10 SYSTEM AND METHOD FOR TRANSMITTING DATA IN AN ELECTRONIC CIRCUIT

Publications (1)

Publication Number Publication Date
ATE415742T1 true ATE415742T1 (en) 2008-12-15

Family

ID=34982454

Family Applications (1)

Application Number Title Priority Date Filing Date
AT05291515T ATE415742T1 (en) 2005-06-10 2005-07-13 DATA TRANSMISSION SYSTEM AND METHOD IN AN ELECTRONIC CIRCUIT

Country Status (5)

Country Link
US (1) US20070002634A1 (en)
EP (1) EP1732241B1 (en)
AT (1) ATE415742T1 (en)
DE (1) DE602005011262D1 (en)
FR (1) FR2887093B1 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2890766B1 (en) * 2005-09-12 2007-11-30 Arteris Sa SYSTEM AND METHOD FOR ASYNCHRONOUS CIRCUIT COMMUNICATION BETWEEN SYNCHRONOUS SUB-CIRCUITS
FR2899413B1 (en) * 2006-03-31 2008-08-08 Arteris Sa MESSAGE SWITCHING SYSTEM
FR2900017B1 (en) * 2006-04-12 2008-10-31 Arteris Sa EXTERNAL CHIP FUNCTIONAL BLOCK INTERCONNECTION SYSTEM PROVIDED WITH A SINGLE COMMUNICATION PARAMETRABLE PROTOCOL
FR2901437B1 (en) * 2006-05-16 2008-08-08 Arteris Sa METHOD FOR MAKING A SYNCHRONIZATION CIRCUIT OF ASYNCHRONOUSLY EXCHANGED DATA BETWEEN TWO SYNCHRONOUS BLOCKS, AND SYNCHRONIZATION CIRCUIT PRODUCED BY SUCH A METHOD
FR2902957B1 (en) * 2006-06-23 2008-09-12 Arteris Sa SYSTEM AND METHOD FOR MANAGING MESSAGES TRANSMITTED IN AN INTERCONNECTION NETWORK
FR2904445B1 (en) * 2006-07-26 2008-10-10 Arteris Sa SYSTEM FOR MANAGING MESSAGES TRANSMITTED IN A CHIP INTERCONNECTION NETWORK
JP6345396B2 (en) * 2013-08-27 2018-06-20 シャープ株式会社 Wireless equipment band and radio

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2243851A (en) * 1940-06-06 1941-06-03 Bell Telephone Labor Inc Wire line transmission
US5764093A (en) * 1981-11-28 1998-06-09 Advantest Corporation Variable delay circuit
KR970005124B1 (en) * 1991-08-14 1997-04-12 가부시끼가이샤 아드반테스트 Variable delay circuit
US5306967A (en) * 1992-05-29 1994-04-26 Integrated Device Technology, Inc. Apparatus for improving signal transmission along parallel lines
JPH0613857A (en) * 1992-06-25 1994-01-21 Fujitsu Ltd Delay adjustment circuit
US5544203A (en) * 1993-02-17 1996-08-06 Texas Instruments Incorporated Fine resolution digital delay line with coarse and fine adjustment stages
JP2771464B2 (en) * 1994-09-29 1998-07-02 日本電気アイシーマイコンシステム株式会社 Digital PLL circuit
DE69615471T2 (en) * 1995-07-07 2002-05-08 Sun Microsystems, Inc. Method and device for the dynamic calculation of filling levels of a synchronous FIFO buffer
US5994946A (en) * 1996-10-31 1999-11-30 Metaflow Technologies, Inc. Alternating inverters for capacitive coupling reduction in transmission lines
US6211739B1 (en) * 1997-06-03 2001-04-03 Cypress Semiconductor Corp. Microprocessor controlled frequency lock loop for use with an external periodic signal
JP3560780B2 (en) * 1997-07-29 2004-09-02 富士通株式会社 Variable delay circuit and semiconductor integrated circuit device
US6239615B1 (en) * 1998-01-21 2001-05-29 Altera Corporation High-performance interconnect
US6008705A (en) * 1998-02-26 1999-12-28 International Business Machines Corporation Crosstalk suppression in wide, high-speed buses
US6260152B1 (en) * 1998-07-30 2001-07-10 Siemens Information And Communication Networks, Inc. Method and apparatus for synchronizing data transfers in a logic circuit having plural clock domains
US6342823B1 (en) * 1998-08-26 2002-01-29 International Business Machines Corp. System and method for reducing calculation complexity of lossy, frequency-dependent transmission-line computation
US6414542B2 (en) * 1999-03-17 2002-07-02 Koninklijke Philips Electronics N.V. Integrated circuit with relative sense inversion of signals along adjacent parallel signal paths
US6389581B1 (en) * 1999-07-16 2002-05-14 Silicone Graphics Inc. Optimizing repeaters positioning along interconnects
JP2001084763A (en) * 1999-09-08 2001-03-30 Mitsubishi Electric Corp Clock generation circuit and semiconductor memory device having the same
US6661303B1 (en) * 1999-11-30 2003-12-09 International Business Machines Corporation Cross talk suppression in a bidirectional bus
US20040128413A1 (en) * 2001-06-08 2004-07-01 Tiberiu Chelcea Low latency fifo circuits for mixed asynchronous and synchronous systems
JP2002373039A (en) * 2001-06-18 2002-12-26 Mitsubishi Electric Corp Bus circuit and bus circuit design method
US6759911B2 (en) * 2001-11-19 2004-07-06 Mcron Technology, Inc. Delay-locked loop circuit and method using a ring oscillator and counter-based delay
US6703868B2 (en) * 2001-12-20 2004-03-09 Hyperchip Inc. Methods, apparatus, and systems for reducing interference on nearby conductors
US6915361B2 (en) * 2002-10-03 2005-07-05 International Business Machines Corporation Optimal buffered routing path constructions for single and multiple clock domains systems
US6812760B1 (en) * 2003-07-02 2004-11-02 Micron Technology, Inc. System and method for comparison and compensation of delay variations between fine delay and coarse delay circuits
FR2860663B1 (en) * 2003-10-01 2006-09-01 Arteris DIGITAL DELAY DEVICE, DIGITAL OSCILLATOR CLOCK SIGNAL GENERATOR, AND MEMORY INTERFACE

Also Published As

Publication number Publication date
EP1732241A1 (en) 2006-12-13
US20070002634A1 (en) 2007-01-04
EP1732241B1 (en) 2008-11-26
DE602005011262D1 (en) 2009-01-08
FR2887093A1 (en) 2006-12-15
FR2887093B1 (en) 2007-08-31

Similar Documents

Publication Publication Date Title
DE60308183D1 (en) BUFFER ARRANGEMENT FOR MEMORY
WO2006018843A3 (en) A system and method for the synchronization of data across multiple computing devices
WO2008094433A3 (en) Method and apparatus to store data patterns
TW200708115A (en) Parallel execution of media encoding using multi-threaded single instruction multiple data processing
ATE399413T1 (en) DATA TRANSFER WITH SHARED DATA STREAM AND MULTIPLE ACCESS POINTS
DE60324255D1 (en) WEGUNGSVEKTORMERKMALEN
WO2008105898A3 (en) Reconfigurable data processing system
ATE415742T1 (en) DATA TRANSMISSION SYSTEM AND METHOD IN AN ELECTRONIC CIRCUIT
DE602006002022D1 (en) Method and device for data transmission between USB customers
NO20083721L (en) High speed redundant data processing system
ATE309564T1 (en) ARRANGEMENT FOR OPERATING FIELD DEVICES OF AN OPERATING SYSTEM OF A BUILDING
MX2009003641A (en) Systems and methods for contracting with multiple parties.
ATE469486T1 (en) ROUTING DEVICE FOR A UNDER SEA ELECTRONICS MODULE
TW200745874A (en) Computer and main circuit board thereof
ATE458333T1 (en) ROUTING DEVICE FOR A UNDER SEA ELECTRONICS MODULE
ATE394739T1 (en) COUPLING DEVICE FOR CONNECTING DEVICES TO A BUS SYSTEM
ATE469397T1 (en) INTEGRATED CIRCUIT AND METHOD FOR TRANSACTION WITHDRAWAL
ATE516566T1 (en) DATA TRANSFER BETWEEN MODULES
ATE458332T1 (en) CIRCUIT ARRANGEMENT AND METHOD FOR OPERATING SUCH A CIRCUIT ARRANGEMENT
ATE512408T1 (en) STRUCTURE AND METHODS FOR DATA STORAGE AND RETRIEVAL
SE0303058D0 (en) Methods and arrangements in an information management system
DE502005002830D1 (en) ELECTRONIC MODULE AND METHOD FOR THE PRODUCTION THEREOF
ATE525699T1 (en) CONNECTING NETWORK WITH DYNAMIC SUBNETWORKS
DE602005000982D1 (en) A device for protecting low / high order traffic cards in a synchronous digital hierarchy transmission device
ATE480785T1 (en) DEVICE FOR DETERMINING THE OWN SPEED OF A WATERCRAFT

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties