ATE421149T1 - Integrierte schaltung mit einer selbsttesteinrichtung für einen eingebetteten nichtflüchtigen speicher und verwandte testverfahren - Google Patents

Integrierte schaltung mit einer selbsttesteinrichtung für einen eingebetteten nichtflüchtigen speicher und verwandte testverfahren

Info

Publication number
ATE421149T1
ATE421149T1 AT02724563T AT02724563T ATE421149T1 AT E421149 T1 ATE421149 T1 AT E421149T1 AT 02724563 T AT02724563 T AT 02724563T AT 02724563 T AT02724563 T AT 02724563T AT E421149 T1 ATE421149 T1 AT E421149T1
Authority
AT
Austria
Prior art keywords
test
testing
embedded memory
memory
embedded
Prior art date
Application number
AT02724563T
Other languages
English (en)
Inventor
Steffen Gappisch
Georg Farkas
Original Assignee
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv filed Critical Nxp Bv
Application granted granted Critical
Publication of ATE421149T1 publication Critical patent/ATE421149T1/de

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/30Accessing single arrays
    • G11C29/32Serial access; Scan testing
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/20Address generation devices; Devices for accessing memories, e.g. details of addressing circuits using counters or linear-feedback shift registers [LFSR]
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38Response verification devices
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2207/00Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10Aspects relating to interfaces of memory device to external buses
    • G11C2207/104Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs

Landscapes

  • Tests Of Electronic Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
  • Non-Volatile Memory (AREA)
  • Microcomputers (AREA)
AT02724563T 2001-04-25 2002-04-22 Integrierte schaltung mit einer selbsttesteinrichtung für einen eingebetteten nichtflüchtigen speicher und verwandte testverfahren ATE421149T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP01110213 2001-04-25

Publications (1)

Publication Number Publication Date
ATE421149T1 true ATE421149T1 (de) 2009-01-15

Family

ID=8177247

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02724563T ATE421149T1 (de) 2001-04-25 2002-04-22 Integrierte schaltung mit einer selbsttesteinrichtung für einen eingebetteten nichtflüchtigen speicher und verwandte testverfahren

Country Status (7)

Country Link
US (1) US6876591B2 (de)
EP (1) EP1388150B1 (de)
JP (1) JP2004520673A (de)
CN (1) CN100442395C (de)
AT (1) ATE421149T1 (de)
DE (1) DE60230865D1 (de)
WO (1) WO2002086907A1 (de)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030225567A1 (en) * 2002-03-09 2003-12-04 Koch Stefan Marco System and method for emulating an embedded non-volatile memory
KR100442878B1 (ko) * 2002-07-08 2004-08-02 삼성전자주식회사 온 칩 롬 테스트 장치 및 방법
CN100356481C (zh) * 2004-01-30 2007-12-19 北京中星微电子有限公司 一种嵌入式存储器的测试装置
CN100334558C (zh) * 2004-03-23 2007-08-29 上海华虹集成电路有限责任公司 监控仿真芯片内部eeprom的方法
CN100369159C (zh) * 2004-07-20 2008-02-13 中兴通讯股份有限公司 一种闪存存储器的检测方法
US20060090105A1 (en) * 2004-10-27 2006-04-27 Woods Paul R Built-in self test for read-only memory including a diagnostic mode
TWI260641B (en) * 2005-01-06 2006-08-21 Prolific Technology Inc Method for storing compare data in a read-only memory built-in self-test circuit
US7617425B2 (en) * 2005-06-27 2009-11-10 Logicvision, Inc. Method for at-speed testing of memory interface using scan
EP2016494A4 (de) * 2006-02-14 2010-02-03 Atmel Corp Beschreiben und einstellen von flash-speichern
US7610528B2 (en) * 2006-02-14 2009-10-27 Atmel Corporation Configuring flash memory
KR101028901B1 (ko) * 2009-02-05 2011-04-12 (주)인디링스 메모리 장치, 메모리 관리 장치 및 메모리 관리 방법
CN102237145A (zh) * 2010-04-22 2011-11-09 联咏科技股份有限公司 箝入式存储装置以及其测试方法
CN103325421B (zh) * 2012-03-23 2016-02-10 上海华虹宏力半导体制造有限公司 非挥发性存储器棋盘格测试电路及其检测方法
CN103093834B (zh) * 2013-01-28 2016-11-16 上海华虹宏力半导体制造有限公司 闪存的可靠性测试方法
US9773570B2 (en) 2013-03-06 2017-09-26 International Business Machines Corporation Built-in-self-test (BIST) test time reduction
CN103700408B (zh) * 2014-01-07 2017-03-29 上海华虹宏力半导体制造有限公司 存储器的检测方法
US10002044B2 (en) 2014-08-19 2018-06-19 Samsung Electronics Co., Ltd. Memory devices and modules
KR102214556B1 (ko) * 2014-08-19 2021-02-09 삼성전자주식회사 메모리 장치 및 모듈
KR20160071769A (ko) * 2014-12-12 2016-06-22 삼성전자주식회사 반도체 메모리 장치 및 이를 포함하는 메모리 시스템
CN105572565B (zh) * 2015-12-23 2018-08-24 中国电子科技集团公司第五十八研究所 适用于1553总线协议的内建自测试电路
CN106556793B (zh) * 2016-11-09 2019-05-31 上海东软载波微电子有限公司 芯片测试系统及测试方法
CN110751978B (zh) * 2019-10-16 2021-06-08 上海华虹宏力半导体制造有限公司 用于非挥发性存储器的测试校调方法及测试校调电路
US11347585B2 (en) * 2020-07-10 2022-05-31 Micron Technology, Inc. Compression method for defect visibility in a memory device

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5173906A (en) * 1990-08-31 1992-12-22 Dreibelbis Jeffrey H Built-in self test for integrated circuits
US5883843A (en) * 1996-04-30 1999-03-16 Texas Instruments Incorporated Built-in self-test arrangement for integrated circuit memory devices
US5677913A (en) * 1996-07-01 1997-10-14 Sun Microsystems, Inc. Method and apparatus for efficient self testing of on-chip memory
US5946245A (en) * 1996-11-27 1999-08-31 Texas Instruments Incorporated Memory array test circuit and method
JP2000030483A (ja) * 1998-07-15 2000-01-28 Mitsubishi Electric Corp 大規模メモリ用bist回路
KR100308621B1 (ko) * 1998-11-19 2001-12-17 윤종용 반도체 메모리 장치를 위한 프로그램 가능한 내장 자기 테스트 시스템
US6651202B1 (en) * 1999-01-26 2003-11-18 Lsi Logic Corporation Built-in self repair circuitry utilizing permanent record of defects

Also Published As

Publication number Publication date
WO2002086907A1 (en) 2002-10-31
CN100442395C (zh) 2008-12-10
EP1388150B1 (de) 2009-01-14
CN1462451A (zh) 2003-12-17
JP2004520673A (ja) 2004-07-08
EP1388150A1 (de) 2004-02-11
DE60230865D1 (de) 2009-03-05
US20040109370A1 (en) 2004-06-10
US6876591B2 (en) 2005-04-05

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