ATE423379T1 - Verfahren zum betreiben einer datenspeichervorrichtung unter verwendung von passivmatrixadressierung - Google Patents

Verfahren zum betreiben einer datenspeichervorrichtung unter verwendung von passivmatrixadressierung

Info

Publication number
ATE423379T1
ATE423379T1 AT04808855T AT04808855T ATE423379T1 AT E423379 T1 ATE423379 T1 AT E423379T1 AT 04808855 T AT04808855 T AT 04808855T AT 04808855 T AT04808855 T AT 04808855T AT E423379 T1 ATE423379 T1 AT E423379T1
Authority
AT
Austria
Prior art keywords
data storage
addressing
storage cells
segment
passive matrix
Prior art date
Application number
AT04808855T
Other languages
English (en)
Inventor
Per Hamberg
Christer Karlsson
Per-Erik Nordal
Nicklas Ojakangas
Johan Carlsson
Hans Gudesen
Original Assignee
Thin Film Electronics Asa
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thin Film Electronics Asa filed Critical Thin Film Electronics Asa
Application granted granted Critical
Publication of ATE423379T1 publication Critical patent/ATE423379T1/de

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/06—Address interface arrangements, e.g. address buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1032—Reliability improvement, data loss prevention, degraded operation etc
    • G06F2212/1036—Life time enhancement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7211—Wear leveling
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G11C2013/0083—Write to perform initialising, forming process, electro forming or conditioning

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)
  • Storing Facsimile Image Data (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
AT04808855T 2003-11-24 2004-11-24 Verfahren zum betreiben einer datenspeichervorrichtung unter verwendung von passivmatrixadressierung ATE423379T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NO20035225A NO324607B1 (no) 2003-11-24 2003-11-24 Fremgangsmate for a betjene et datalagringsapparat som benytter passiv matriseadressering

Publications (1)

Publication Number Publication Date
ATE423379T1 true ATE423379T1 (de) 2009-03-15

Family

ID=30439586

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04808855T ATE423379T1 (de) 2003-11-24 2004-11-24 Verfahren zum betreiben einer datenspeichervorrichtung unter verwendung von passivmatrixadressierung

Country Status (12)

Country Link
US (2) US7352612B2 (de)
EP (1) EP1690260B1 (de)
JP (1) JP4540676B2 (de)
KR (1) KR20060097743A (de)
CN (1) CN1906697B (de)
AT (1) ATE423379T1 (de)
AU (1) AU2004292125A1 (de)
CA (1) CA2546263A1 (de)
DE (1) DE602004019561D1 (de)
NO (1) NO324607B1 (de)
RU (1) RU2320032C1 (de)
WO (1) WO2005050657A1 (de)

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NO324607B1 (no) * 2003-11-24 2007-11-26 Thin Film Electronics Asa Fremgangsmate for a betjene et datalagringsapparat som benytter passiv matriseadressering
JP4420351B2 (ja) * 2005-09-30 2010-02-24 富士通株式会社 階層ストレージシステム、制御方法及びプログラム
US7730258B1 (en) 2005-11-01 2010-06-01 Netapp, Inc. System and method for managing hard and soft lock state information in a distributed storage system environment
JP4229140B2 (ja) * 2006-06-16 2009-02-25 ソニー株式会社 集積回路チップ、データ読み出し方法、データ書き込み方法、ｉｃカード、および携帯電話機
US7916544B2 (en) 2008-01-25 2011-03-29 Micron Technology, Inc. Random telegraph signal noise reduction scheme for semiconductor memories
US7974119B2 (en) 2008-07-10 2011-07-05 Seagate Technology Llc Transmission gate-based spin-transfer torque memory unit
US7885097B2 (en) * 2008-10-10 2011-02-08 Seagate Technology Llc Non-volatile memory array with resistive sense element block erase and uni-directional write
US9030867B2 (en) 2008-10-20 2015-05-12 Seagate Technology Llc Bipolar CMOS select device for resistive sense memory
US7936580B2 (en) 2008-10-20 2011-05-03 Seagate Technology Llc MRAM diode array and access method
US8045412B2 (en) * 2008-10-21 2011-10-25 Seagate Technology Llc Multi-stage parallel data transfer
US7936583B2 (en) 2008-10-30 2011-05-03 Seagate Technology Llc Variable resistive memory punchthrough access method
US7916513B2 (en) * 2008-11-05 2011-03-29 Seagate Technology Llc Non-destructive read back for ferroelectric data storage device
US7825478B2 (en) 2008-11-07 2010-11-02 Seagate Technology Llc Polarity dependent switch for resistive sense memory
US8178864B2 (en) 2008-11-18 2012-05-15 Seagate Technology Llc Asymmetric barrier diode
US8203869B2 (en) 2008-12-02 2012-06-19 Seagate Technology Llc Bit line charge accumulation sensing for resistive changing memory
US8040713B2 (en) * 2009-01-13 2011-10-18 Seagate Technology Llc Bit set modes for a resistive sense memory cell array
US7944729B2 (en) * 2009-01-28 2011-05-17 Seagate Technology Llc Simultaneously writing multiple addressable blocks of user data to a resistive sense memory cell array
KR101034405B1 (ko) * 2009-05-06 2011-05-12 이정복 여드름 피부 개선용 화장료 조성물
US8159856B2 (en) 2009-07-07 2012-04-17 Seagate Technology Llc Bipolar select device for resistive sense memory
US8158964B2 (en) 2009-07-13 2012-04-17 Seagate Technology Llc Schottky diode switch and memory units containing the same
US8648426B2 (en) 2010-12-17 2014-02-11 Seagate Technology Llc Tunneling transistors
CN103297446B (zh) * 2012-02-23 2016-10-12 腾讯科技（深圳）有限公司 游戏资源分配的方法及服务器
FR2993380B1 (fr) * 2012-07-10 2020-05-15 Morpho Procede pour proteger une carte a puce contre une attaque physique destinee a modifier le comportement logique d'un programme fonctionnel
CN103996412A (zh) * 2013-02-19 2014-08-20 北京同方微电子有限公司 一种用于智能卡非易失性存储器的掉电保护方法
JP6121857B2 (ja) 2013-09-20 2017-04-26 株式会社東芝 メモリシステム
US10504588B2 (en) * 2015-05-12 2019-12-10 Alacrity Semiconductors, Inc. Multi-level versatile memory
KR102602694B1 (ko) * 2015-12-15 2023-11-15 삼성전자주식회사 스토리지 컨트롤러의 작동 방법과 이를 포함하는 스토리지 장치의 작동 방법
US9613676B1 (en) * 2016-06-29 2017-04-04 Micron Technology, Inc. Writing to cross-point non-volatile memory
CN109189694B (zh) * 2018-07-28 2020-09-08 华中科技大学 一种scm的数据编码方法及数据存储方法
KR102480013B1 (ko) * 2018-11-26 2022-12-22 삼성전자 주식회사 누설 전류를 보상하는 메모리 장치 및 이의 동작 방법
US10998080B2 (en) * 2019-09-24 2021-05-04 Micron Technology, Inc. Imprint recovery for memory cells

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RU2127005C1 (ru) * 1993-01-27 1999-02-27 Самсунг Электроникс Ко., Лтд. Полупроводниковый прибор и способ его изготовления (варианты)
RU2143752C1 (ru) * 1998-10-23 1999-12-27 Мохнатюк Александр Анатольевич Способ создания трехмерной оптической памяти
JP4344450B2 (ja) * 2000-02-25 2009-10-14 Ｏｋｉセミコンダクタ株式会社 不揮発性メモリ
NO312699B1 (no) * 2000-07-07 2002-06-17 Thin Film Electronics Asa Adressering av minnematrise
NO20004236L (no) * 2000-08-24 2002-02-25 Thin Film Electronics Asa Ikke-flyktig passiv matriseinnretning og fremgangsmåte for utlesing av samme
NO312698B1 (no) * 2000-07-07 2002-06-17 Thin Film Electronics Asa Fremgangsmåte til å utföre skrive- og leseoperasjoner i en passiv matriseminne og apparat for å utföre fremgangsmåten
DE10038925A1 (de) * 2000-08-09 2002-03-14 Infineon Technologies Ag Elektronische Treiberschaltung für Wortleitungen einer Speichermatrix und Speichervorrichtung
NO312928B1 (no) * 2001-02-26 2002-07-15 Thin Film Electronics Asa Ikke-destruktiv utlesing
JP2002278850A (ja) * 2001-03-14 2002-09-27 Nec Corp 半導体装置
NO20015879A (no) * 2001-11-30 2003-03-31 Thin Film Electronics Asa Fremgangsmåte til lesing av celler i en passiv matriseadresserbar innretning, samt innretning for utførelse av fremgangsmåten
NO317905B1 (no) * 2002-09-11 2004-12-27 Thin Film Electronics Asa Fremgangsmate for a operere ferroelektrisk eller elektret minneinnretning og en innretning av denne art
US6922350B2 (en) * 2002-09-27 2005-07-26 Intel Corporation Reducing the effect of write disturbs in polymer memories
NO324607B1 (no) * 2003-11-24 2007-11-26 Thin Film Electronics Asa Fremgangsmate for a betjene et datalagringsapparat som benytter passiv matriseadressering
US7215565B2 (en) * 2005-01-04 2007-05-08 Thin Film Electronics Asa Method for operating a passive matrix-addressable ferroelectric or electret memory device

Also Published As

Publication number Publication date
AU2004292125A1 (en) 2005-06-02
NO20035225D0 (no) 2003-11-24
CN1906697B (zh) 2010-05-05
US20080151609A1 (en) 2008-06-26
DE602004019561D1 (de) 2009-04-02
US7352612B2 (en) 2008-04-01
US7646629B2 (en) 2010-01-12
EP1690260A1 (de) 2006-08-16
CA2546263A1 (en) 2005-06-02
WO2005050657A1 (en) 2005-06-02
KR20060097743A (ko) 2006-09-14
NO324607B1 (no) 2007-11-26
JP4540676B2 (ja) 2010-09-08
US20070103960A1 (en) 2007-05-10
RU2320032C1 (ru) 2008-03-20
CN1906697A (zh) 2007-01-31
NO20035225L (no) 2005-05-25
JP2007512655A (ja) 2007-05-17
EP1690260B1 (de) 2009-02-18

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