ATE428225T1 - Faltungskodierer wobei ein geanderter multiplizierer verwendet wird - Google Patents

Faltungskodierer wobei ein geanderter multiplizierer verwendet wird

Info

Publication number
ATE428225T1
ATE428225T1 AT01310694T AT01310694T ATE428225T1 AT E428225 T1 ATE428225 T1 AT E428225T1 AT 01310694 T AT01310694 T AT 01310694T AT 01310694 T AT01310694 T AT 01310694T AT E428225 T1 ATE428225 T1 AT E428225T1
Authority
AT
Austria
Prior art keywords
multiplier
modified
convolutional coding
function
coding
Prior art date
Application number
AT01310694T
Other languages
English (en)
Inventor
Peter Richard Dent
Original Assignee
Texas Instruments Inc
Texas Instruments Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc, Texas Instruments Ltd filed Critical Texas Instruments Inc
Application granted granted Critical
Publication of ATE428225T1 publication Critical patent/ATE428225T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
    • G06F7/724—Finite field arithmetic
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/23—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using convolutional codes, e.g. unit memory codes

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Error Detection And Correction (AREA)
  • Mobile Radio Communication Systems (AREA)
AT01310694T 2001-12-20 2001-12-20 Faltungskodierer wobei ein geanderter multiplizierer verwendet wird ATE428225T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP01310694A EP1322042B1 (de) 2001-12-20 2001-12-20 Faltungskodierer wobei ein geänderter Multiplizierer verwendet wird

Publications (1)

Publication Number Publication Date
ATE428225T1 true ATE428225T1 (de) 2009-04-15

Family

ID=8182557

Family Applications (1)

Application Number Title Priority Date Filing Date
AT01310694T ATE428225T1 (de) 2001-12-20 2001-12-20 Faltungskodierer wobei ein geanderter multiplizierer verwendet wird

Country Status (4)

Country Link
US (1) US7039852B2 (de)
EP (1) EP1322042B1 (de)
AT (1) ATE428225T1 (de)
DE (1) DE60138290D1 (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6973579B2 (en) 2002-05-07 2005-12-06 Interdigital Technology Corporation Generation of user equipment identification specific scrambling code for the high speed shared control channel
DE10336121B4 (de) * 2003-08-06 2006-10-26 Infineon Technologies Ag Serielle asynchrone Schnittstelle mit SLIP-Kodierung/Dekodierung und CRC-Prüfung im Sende- und Empfangspfad
US20050094551A1 (en) * 2003-09-25 2005-05-05 Broadcom Corporation Processor instruction for DMT encoding
US7305608B2 (en) * 2003-09-25 2007-12-04 Broadcom Corporation DSL trellis encoding
US7751557B2 (en) * 2003-09-26 2010-07-06 Broadcom Corporation Data de-scrambler
US7580412B2 (en) * 2003-09-26 2009-08-25 Broadcom Corporation System and method for generating header error control byte for Asynchronous Transfer Mode cell
US7903810B2 (en) * 2003-09-26 2011-03-08 Broadcom Corporation Single instruction for data scrambling
US7734041B2 (en) * 2003-09-26 2010-06-08 Broadcom Corporation System and method for de-scrambling and bit-order-reversing payload bytes in an Asynchronous Transfer Mode cell
US7756273B2 (en) * 2003-09-26 2010-07-13 Broadcom Corporation System and method for bit-reversing and scrambling payload bytes in an asynchronous transfer mode cell
DE10359268B4 (de) * 2003-12-17 2011-05-19 Infineon Technologies Ag Vorrichtung zum Erzeugen von Sendesignalen in einer Mobilfunkstation mittels eines Verwürfelungscode-Generators für Präambeln und für Sendesignale dedizierter physikalischer Kanäle
US8000377B2 (en) * 2004-05-24 2011-08-16 General Dynamics C4 Systems, Inc. System and method for variable rate multiple access short message communications
US20070223572A1 (en) * 2006-03-24 2007-09-27 Samsung Electronics Co., Ltd. Method and system of pixel interleaving for improving video signal transmission quality in wireless communication
US8194750B2 (en) 2006-10-16 2012-06-05 Samsung Electronics Co., Ltd. System and method for digital communication having a circulant bit interleaver for equal error protection (EEP) and unequal error protection (UEP)
US10216567B1 (en) * 2018-08-22 2019-02-26 Avago Technologies International Sales Pte. Limited Direct parity encoder
US11979207B2 (en) * 2021-06-03 2024-05-07 Cornell University Sparsity-adaptive equalization for communication systems

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3678469A (en) * 1970-12-01 1972-07-18 Ibm Universal cyclic division circuit
JPS5949640A (ja) * 1982-09-16 1984-03-22 Toshiba Corp 乗算回路
JP3351413B2 (ja) * 2000-03-01 2002-11-25 日本電気株式会社 並列処理リードソロモン符号化回路及びそれに用いる並列処理リードソロモン符号化方法
JP2001298370A (ja) * 2000-04-13 2001-10-26 Matsushita Electric Ind Co Ltd 符号化装置

Also Published As

Publication number Publication date
US20030120994A1 (en) 2003-06-26
DE60138290D1 (de) 2009-05-20
EP1322042A1 (de) 2003-06-25
EP1322042B1 (de) 2009-04-08
US7039852B2 (en) 2006-05-02

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