ATE440330T1 - Verfahren und anordnung mit speicherprotokol zur speicherverbindung - Google Patents

Verfahren und anordnung mit speicherprotokol zur speicherverbindung

Info

Publication number
ATE440330T1
ATE440330T1 AT04734273T AT04734273T ATE440330T1 AT E440330 T1 ATE440330 T1 AT E440330T1 AT 04734273 T AT04734273 T AT 04734273T AT 04734273 T AT04734273 T AT 04734273T AT E440330 T1 ATE440330 T1 AT E440330T1
Authority
AT
Austria
Prior art keywords
memory
connection
arrangement
protocol
memory component
Prior art date
Application number
AT04734273T
Other languages
English (en)
Inventor
Matti Floman
Kimmo Mylly
Original Assignee
Spyder Navigations Llc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Spyder Navigations Llc filed Critical Spyder Navigations Llc
Application granted granted Critical
Publication of ATE440330T1 publication Critical patent/ATE440330T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Memory System (AREA)
  • Communication Control (AREA)
  • Debugging And Monitoring (AREA)
  • Bus Control (AREA)
AT04734273T 2003-05-22 2004-05-21 Verfahren und anordnung mit speicherprotokol zur speicherverbindung ATE440330T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FI20035072A FI20035072A0 (fi) 2003-05-22 2003-05-22 Liitäntäväylä, elektroniikkalaite ja järjestelmä
PCT/FI2004/050074 WO2004109529A1 (en) 2003-05-22 2004-05-21 A connection bus, an electronic device, and a system

Publications (1)

Publication Number Publication Date
ATE440330T1 true ATE440330T1 (de) 2009-09-15

Family

ID=8566406

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04734273T ATE440330T1 (de) 2003-05-22 2004-05-21 Verfahren und anordnung mit speicherprotokol zur speicherverbindung

Country Status (9)

Country Link
US (1) US7430625B2 (de)
EP (1) EP1625507B1 (de)
JP (2) JP2006526213A (de)
KR (1) KR100666086B1 (de)
CN (1) CN100483376C (de)
AT (1) ATE440330T1 (de)
DE (1) DE602004022658D1 (de)
FI (1) FI20035072A0 (de)
WO (1) WO2004109529A1 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
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EP2141634A4 (de) * 2007-04-20 2011-11-02 Panasonic Corp Einfügungs-/entfernungsdetektor
US7843225B2 (en) * 2009-04-14 2010-11-30 Via Technologies, Inc. Protocol-based bus termination for multi-core processors
JP5859663B2 (ja) * 2011-10-17 2016-02-10 インテル コーポレイション 接続を行うためのシステム、ｉｏコネクタアセンブリ及び動作方法
JP5884106B2 (ja) * 2011-12-22 2016-03-15 日本電産サンキョー株式会社 Ｉｃカードリーダ及びインタフェースｉｃ判別方法
CN104268110B (zh) * 2014-09-15 2018-10-12 联想(北京)有限公司 一种设备识别方法、处理器和设备识别系统
JP2018022383A (ja) 2016-08-04 2018-02-08 東芝メモリ株式会社 メモリシステム
US10366033B2 (en) * 2016-09-15 2019-07-30 General Electric Company Automated retrofit installation tool for replacement of one or more pre-existing dedicated input/output (I/O) modules and terminal boards with one or more universal I/O modules
CN108563602A (zh) * 2018-01-02 2018-09-21 联想(北京)有限公司 电子设备及信息传输方法
US12339800B2 (en) * 2023-05-31 2025-06-24 Infineon Technologies Canada Inc. Package and integrated circuit with interface detection
JP7754969B2 (ja) * 2024-03-06 2025-10-15 日立ヴァンタラ株式会社 インタフェースモジュール、情報通信装置、起動方法

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JPH08286925A (ja) * 1995-04-11 1996-11-01 Toshiba Corp プログラムロード方法およびそのプログラムロード方法を使用したパーソナルコンピュータ
JPH11505049A (ja) * 1995-05-09 1999-05-11 スマートムーブ （エヌジー） リミテッド カード・インターフェース
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JP3565686B2 (ja) * 1997-08-01 2004-09-15 東京エレクトロンデバイス株式会社 コンピュータの記憶装置及び変換システム
US6138180A (en) * 1997-09-12 2000-10-24 Symbol Technologies, Inc. Adaptive computer peripheral for selecting a communications protocol by cycling through a plurality of given protocols
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JP4649009B2 (ja) * 2000-03-08 2011-03-09 株式会社東芝 カードインタフェースを備えた情報処理装置、同装置に装着可能なカード型電子機器、及び同装置におけ動作モード設定方法
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Also Published As

Publication number Publication date
CN100483376C (zh) 2009-04-29
JP5364036B2 (ja) 2013-12-11
WO2004109529A1 (en) 2004-12-16
KR100666086B1 (ko) 2007-01-09
EP1625507B1 (de) 2009-08-19
CN1795443A (zh) 2006-06-28
FI20035072A0 (fi) 2003-05-22
KR20060004993A (ko) 2006-01-16
JP2010282617A (ja) 2010-12-16
US7430625B2 (en) 2008-09-30
DE602004022658D1 (de) 2009-10-01
JP2006526213A (ja) 2006-11-16
US20040268077A1 (en) 2004-12-30
EP1625507A1 (de) 2006-02-15

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